HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 858

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 LCD Controller
5. Packed 2bpp (Pixel Alignment in Byte is Little Endian)
6. Packed 4bpp (Pixel Alignment in Byte is Little Endian)
7. Unpacked 4bpp [Windows CE Recommended Format]
8. Unpacked 5bpp [Windows CE Recommended Format]
Rev.6.00 Mar. 27, 2009 Page 800 of 1036
REJ09B0254-0600
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
MSB
MSB
MSB
MSB
P03
P07
P13
P17
7
7
7
7
6
6
6
6
P01
P04
P06
P11
P13
P15
Display Memory
Display Memory
Display Memory
Display Memory
P02
P06
P12
P16
5
5
5
5
…
…
…
…
…
…
…
…
4
4
4
4
P01
P05
P11
P15
3
3
3
3
P00
P01
P02
P10
P12
P11
2
2
P00
P03
P05
P10
P12
P14
2
P00
P01
P02
P10
P11
P12
2
P00
P04
P10
P14
1
1
1
1
LSB
LSB
LSB
LSB
0
0
0
0
[Bit]
(Byte0)
(Byte1)
[Bit]
(Byte0)
(Byte1)
(Byte2)
[Bit]
(Byte0)
(Byte1)
(Byte2)
[Bit]
(Byte0)
(Byte1)
(Byte2)
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
LAO: Line Address Offset
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
LAO: Line Address Offset
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
LAO: Line Address Offset
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
LAO: Line Address Offset
↓ Top Left Pixel
↓ Top Left Pixel
↓ Top Left Pixel
↓ Top Left Pixel
Pn = Pn[1:0]: Put 2bit data
Pn = Pn[3:0]: Put 4bit data
Pn = Pn[3:0]: Put 4bit data
Pn = Pn[4:0]: Put 5bit data
⎯Unused bits should be 0
⎯Unused bits should be 0
⎯Unused bits should be 0
⎯Unused bits should be 0
Display
Display
Display
Display
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…