HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 476

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.3.5
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 12, Bus State Controller (BSC).
DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled with the clock
pulse (CKIO) falling edge detection or low level detection. When a DREQ input is detected, a
DMAC bus cycle is generated and DMA transfer starts three or more states later.
The second and subsequent DREQ sampling operations are started two cycles after the first
sample.
Operation
• Cycle-Steal Mode
Rev.6.00 Mar. 27, 2009 Page 418 of 1036
REJ09B0254-0600
In cycle-steal mode, the DREQ sampling timing does not change according to the DREQ
detection method, the level detection or edge detection.
For example, as shown in figure 14.17 (cycle-steal mode, level detection), DMA transfer
begins, at the earliest, three cycles after the first sampling is performed. The second sampling
is started two cycles after the first. If DREQ is not detected at this time, sampling is performed
in each subsequent cycle.
Thus, DREQ sampling is performed one step in advance. The third sampling operation is not
performed until the idle cycle following the end of the first DMA transfer.
The above operation is performed continuously for the desired CPU transfer cycles or DMA
transfer cycles, as shown in figures 14.18 and 14.19.
Figures 14.17 and 14.18 show examples in which DACK is output in a read and in a write,
respectively. In both cases, DACK is output for the same period as CSn.
Figure 14.20 shows an example in which sampling is executed in all subsequent cycles when
DREQ cannot be detected. Figure 14.21 shows an example of operation in cycle steal mode
with the edge detection.
Number of Bus Cycle States and DREQ Pin Sampling Timing