HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 638

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Serial Communication Interface with FIFO (SCIF)
Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicates the quantity of data
including a parity error in the received data stored in the receive FIFO data register 2 (SCFRDR2).
The value indicated by the bits 15 to 12 represents the number of parity errors in SCFRDR2.
Bits 11 to 8—Number of Framing Errors 3 to 0 (FER3 to FER0): Indicates the quantity of data
including a framing error in the received data stored in SCFRDR2. The value indicated by bits 11
to 8 represents the number of framing errors in SCFRDR2.
19.2.8
The bit rate register 2 (SCBRR2) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in the serial mode register 2 (SCSMR2),
determines the serial transmit/receive bit rate.
The CPU can always read and write the SCBRR2. The SCBRR2 is initialized to H'FF by a reset or
in module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
The SCBRR2 setting is calculated as follows:
Asynchronous mode:
Rev.6.00 Mar. 27, 2009 Page 580 of 1036
REJ09B0254-0600
Upper 8 bits:
Initial value:
Initial value:
B:
N:
Pφ: Operating frequency for peripheral modules (MHz)
n:
Bit Rate Register 2 (SCBRR2)
N =
R/W:
R/W:
Bit rate (bit/s)
SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255)
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 19.3.)
Bit:
64 × 2
PER3
R/W
15
R
0
7
1
Pφ
2n–1
× B
PER2
R/W
14
R
0
6
1
× 10
6
– 1
PER1
R/W
13
R
0
5
1
PER0
R/W
12
R
0
4
1
FER3
R/W
11
R
0
3
1
FER2
R/W
10
R
0
2
1
FER1
R/W
R
0
1
9
1
FER0
R/W
R
8
0
0
1