HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 459

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

from CMT, a transmit request (TDREQ) and a receive request (RDREQ) from SIOR, and a
transmit request (DREQN1) and a receive request (DREQN0) from USBF. TDREQ, RDREQ,
DREQN1, and DREQN0 are supported for expansion.
When the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, and NMIF = 0) in this mode, a
transfer is started by the transfer request signal input. The source of the transfer request does not
have to be the data transfer source or destination.
When RXI2 is set as a transfer request, however, the transfer source must be the SCIF's receive
data register (RDR2). Likewise, when TXI2 is set as a transfer request, the transfer source must be
the SCIF's transmit data register (TDR2). In addition, when the transfer requester is the A/D
converter, the data transfer source must be the A/D data register (ADDR).
Table 14.4 Selection of On-Chip Module Request Modes Using RS3 to RS0 Bits
RS3
1
Note: * External memory, memory-mapped external device, on-chip supporting module (excluding
RS2
0
1
DMAC, BSC, UBC)
RS1
0
0
0
1
1
RS0
0
0
1
0
1
DMA Transfer Request
Source
Expansion USBF
SCIF transmitter
SCIF receiver
A/D converter
CMT
receiver
USBF
transmitter
SIOF
receiver
SIOF
transmitter
Section 14 Direct Memory Access Controller (DMAC)
DMA Transfer
Request Signal
DREQN[0]
(DMA transfer
request output)
DREQN[1]
(DMA transfer
request output)
RDREQ
(receive-data
transfer request)
TDRQ
(transmit-data
transfer request)
TXI2
(SCIF transmit data
empty interrupt)
RXI2
(SCIF receive data
full interrupt)
ADI
(A/D conversion
end interrupt)
CMI
(Compare-match
timer interrupt)
Rev.6.00 Mar. 27, 2009 Page 401 of 1036
Source
EPDR1
Arbitrary* EPDR2
SIRDR
Arbitrary* SITDR
Arbitrary* TDR2
RDR2
ADDR
Arbitrary* Arbitrary*
Destination Bus Mode
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
REJ09B0254-0600
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Burst/
cycle steal