HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 53

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 On-Chip Oscillation Circuits
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Section 11 Extend Clock Pulse Generator for USB (EXCPG)
Table 11.1
Table 11.2
Section 12 Bus State Controller (BSC)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 12.9
Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment ....................... 320
Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment.......................... 321
Table 12.12 Relationship between Synchronous DRAM type, bus width and AMX ................ 334
Table 12.13 Relationship between LSI Address Pins and
Section 13 Li Bus State Controller (LBSC)
Table 13.1
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.7
Table 14.8
Clock Pulse Generator Pins and Functions............................................................. 261
Register Configuration ........................................................................................... 261
Clock Operating Modes.......................................................................................... 262
Available Combination of Clock Mode and FRQCR Values................................. 264
Register Configuration ........................................................................................... 272
Pin Configuration ................................................................................................... 280
Register Configuration ........................................................................................... 280
Pin Configuration ................................................................................................... 286
Register Configuration ........................................................................................... 288
Physical Address Space Map ................................................................................. 290
Correspondence between External Pins (MD4 and MD3)
and Memory bus width in area0 ............................................................................. 291
SH7727 and PCMCIA Pins.................................................................................... 292
32-Bit External Device/Big Endian Access and Data Alignment .......................... 316
16-Bit External Device/Big Endian Access and Data Alignment .......................... 317
8-Bit External Device/Big Endian Access and Data Alignment ............................ 318
32-Bit External Device/Little Endian Access and Data Alignment ....................... 319
Synchronous DRAM Address Pins ........................................................................ 335
Register Configuration ........................................................................................... 367
Pin Configuration ................................................................................................... 382
DMAC Registers .................................................................................................... 382
Selecting External Request Modes with the RS Bits.............................................. 400
Selection of On-Chip Module Request Modes Using RS3 to RS0 Bits ................. 401
DMA Transfers ...................................................................................................... 405
Relationship of Request Modes and Bus Modes .................................................... 416
Register Configuration ........................................................................................... 432
Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory ............................................................................ 438
Rev.6.00 Mar. 27, 2009 Page li of lvi
REJ09B0254-0600