HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 761

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.5.19 USBDMA Setting Register (USBDMAR)
DMA transfer can be carried out between the endpoint 1 and endpoint 2 data registers by means of
the on-chip DMA controller. Dual address transfer is performed, using byte transfer units. In order
to start DMA transfer, DMA control settings must be made in addition to the settings in this
register.
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 2—Pull-up Enable (PULLUP_E): This bit is for controlling connection notification (D +
pull-up) to the USB host/hub. This bit enables the level of the USB1_pwr_en pin to be controlled.
Writing 1 outputs the High level and 0 outputs the Low level. For more information on the D +
pull-up control, see section 22, USB Pin Multiplex Controller.
Bit 1—Endpoint 2 DMA Transfer Enable (EP2 DMAE): When this bit is set, DMA transfer is
enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of space
in the FIFO buffer, the transfer request signal to the DMA controller is asserted. When 64 bytes
are written to the FIFO buffer in DMA transfer, EP2 packet enabling is set automatically, and 64-
byte data can be transferred. If there is a space in another FIFO, a transfer request is asserted for
the DMA controller again. However, since EP2 packet enable is not set automatically if data
packet size for transfer is less than 64 bytes, set EP2 packet enabling by the CPU with a DMA
transfer end interrupt.
Since EP2-related interrupt requests to the CPU are not masked automatically, interrupt requests
must also be masked as necessary in the interrupt enable register.
Bit 0—Endpoint 1 DMA Transfer Enable (EP1 DMAE): When this bit is set, DMA transfer
can be performed from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte
of space in the FIFO buffer, the transfer request signal to the DMA controller is asserted. When
all received data is read in DMA transfer, the EP1 read-end trigger is performed automatically.
EP1-related interrupt requests to the CPU are not masked automatically.
Initial value:
R/W:
Bit:
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
Rev.6.00 Mar. 27, 2009 Page 703 of 1036
—
R
3
0
Section 23 USB Function Controller
PULLUP_
E
R
2
0
DMAE
REJ09B0254-0600
EP2
R/W
1
0
DMAE
R/W
EP1
0
0