HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 790

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 24 USB HOST Module
24.2.3
HcCommandStatus Register (H'04000408)
The HcCommandStatus register is used by the host controller not only for reflecting the current
status of the host controller, but also for receiving a command issued by the host controller driver.
A write is for setting the host controller driver. The host controller must guarantee that the bit to
which 1 is written to is set and the bit to which 0 is written to is unchanged. The host controller
driver must distribute multiple clear commands to the host controller by a previously issued
command. The host controller driver can read all bits normally.
The SchedulingOverrunCount bit indicates the number of the frame that has detected the
Scheduling Overrun error by the host controller. This occurs when the periodic list has not
completed before EOF. When the Scheduling Overrun error is detected, the host controller
increments the counter and sets SchedulingOverrun in the HcInterruptStatus register.
Register: HcCommandStatus
Bits
31–18
17–16
15–4
3
Rev.6.00 Mar. 27, 2009 Page 732 of 1036
REJ09B0254-0600
HcCommandStatus
Reset
0h
00b
0h
0b
R/W
—
R
—
R/W
Offset: 08–0B
Description
Reserved.
SchedulingOverrunCount (SOC)
These bits are incremented in each SchedulingOverrun error.
These bits are initially set to B'00 and returned to B'11. These
bits are incremented when SchedulingOverrun is detected even
though the SchedulingOverrun bit in HcInterruptStatus is set.
These bits are used by HCD to monitor any continuous
scheduling problem.
Reserved.
OwnershipChangeRequest (OCR)
This bit is set by OS HCD to request the change of the control
of the host controller. When this bit is set, the host controller
sets the OwnershipChange bit in the HcInterruptStatus register.
After a change, this bit is cleared and remains until the next
request from OS HCD.
0: After a change, this bit is cleared and remains until the next
1: Set the OwnershipChange bit in the HcInterruptStatus
request from OS HCD. (initial value)
register.