HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 753

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.5.4
USBEPDR1 is a 128-byte receive FIFO buffer for endpoint 1. USBEPDR1 has a dual-FIFO
configuration, and has a capacity of twice the maximum packet size. When one packet of data is
received normally from the host, EP1 FULL in USB interrupt flag register 0 is set. The number of
receive bytes is indicated in the USBEP1 receive data size register. After the data has been read,
the buffer that was read is enabled to receive again by writing 1 to EP1 RDFN in the USB trigger
register. The receive data in this FIFO buffer can be transferred by DMA (see section 23.5.19,
USBDMA Setting Register (USBDMAR)). This FIFO buffer can be initialized by means of EP1
CLR in the USBFIFO clear register.
23.5.5
USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When transmit data is written
to this FIFO buffer and EP2 PKTE in the USB trigger register is set, one packet of transmit data is
fixed, and the dual-FIFO buffer is switched over. Transmit data for this FIFO buffer can be
transferred by DMA (see section 23.5.19, USBDMA Setting Register (USBDMAR)). This FIFO
buffer can be initialized by means of EP2 CLR in the USBFIFO clear register.
23.5.6
USBEPDR3 is an 8-byte transmit FIFO buffer for endpoint 3, holding one packet of transmit data
in endpoint 3 interrupt transfer. Transmit data is fixed by writing one packet of data and setting
EP3 PKTE in the USB trigger register. When an ACK handshake is received from the host after
one packet of data has been transmitted normally, EP3 TS in the USB interrupt flag register 1 is
set. This FIFO buffer can be initialized by means of EP3 CLR in the USB FIFO clear register.
23.5.7
Together with USB interrupt flag register 1, USBIFR0 indicates interrupt status information
required by the application. When an interrupt source occurs, the corresponding bit is set to 1 and
an interrupt request is sent to the CPU according to the combination with USB interrupt enable
register 0. Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits.
However, EP1 FULL and EP2 EMPTY are status bits, and cannot be cleared.
USBEP1 Data Register (USBEPDR1)
USBEP2 Data Register (USBEPDR2)
USBEP3 Data Register (USBEPDR3)
USB Interrupt Flag Register 0 (USBIFR0)
Rev.6.00 Mar. 27, 2009 Page 695 of 1036
Section 23 USB Function Controller
REJ09B0254-0600