PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 112

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note: The EPIC-1 and SACCO-A must be initialized correctly before the D-channel
Note: The upstream and downstream D-channel arbiter initializations are independent
3.8.5
With EPIC-1, SACCO-A and D-channel arbiter all configured to the system
requirements, the PCM- and CFI-interface can be switched to the operational mode.
The OMDR:OMS1..0 bits must be set (if this has not already be done) to the normal
operation mode (OMS1..0 = 11). When doing this, the PCM-framing interrupt (ISTA:PFI)
will be enabled. If the applied clock and framing signals are in accordance with the
values programmed to the PCM-registers, the PFI-interrupt will be generated (if not
masked). When reading the status register, the STAR:PSS-bit will be set to logical 1.
To enable the PCM-output drivers set OMDR:PSB = 1. The CFI-interface is activated by
programming OMDR:CSB = 1. This enables the output clock and framing signals (DCL
and FSC), if these have been programmed as outputs. It also enables the CFI-output
drivers. The output driver type can be selected between "open drain" and "tristate" with
the OMDR:COS-bit.
Example: Activation of the EPIC-1 part of the ELIC for a typical IOM-2 application:
OMDR = EE
Semiconductor Group
arbiter can operate properly. Particular care must be given to programming the
EPIC-1’s Control Memory (CM) with the required CM-Codes (CMCs).
of each other.
Activation of the PCM- and CFI-Interfaces
H
;
Normal operation mode (OMS1..0 = 11)
PCM-interface active (PSB = 1)
PCM-test loop disabled (PTL = 0)
CFI-output drivers: open drain (COS = 1)
Monitor handshake protocol selected (MFPS = 1)
CFI active (CSB = 1)
Access to EPIC-1 registers via address pins A4..A0 (RBS = 0)
112
Operational Description
PEB 20550
PEF 20550
01.96