PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 371

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PEF20550HV21XT

Manufacturer Part Number
PEF20550HV21XT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF20550HV21XT

Lead Free Status / Rohs Status
Supplier Unconfirmed
The system-specific response delay of the S
y = 1 + 6 = 7.
The delay time experienced by the average S
t = 125 s
(max.) 6 frames delay are due to interface delays and to the ISAC-S waiting for 8 non-
inverted E-bits prior to sending data. This is shown in figure 128 below:
Figure 128
Response Delay of typical S
Semiconductor Group
= (m – 1)[265.625 s
DD
S
Downstream
DD
S
Downstream
S
Upstream
DU
0
0
0
1
/
2
(m – 1)[(
Control Channel First
Set as "Available"
Frame 4
Frame 4
4
IOM Frame 1
R
17
x + 1468.75 s]
/
4
x +
0
Applications according to Figure 127
IOM Frame 5
IOM Frame 5
33
/
2
R
R
) + 7]
5
First non-inverted "E"-Bit
IOM Frame 2
First Valid D-Bit
Sent by ISAC -S
371
R
Control Channel First
Recognized as "Available"
0
6
0
architecture shown in figure 127 is thus
subscriber is then:
R
IOM Frame 6
IOM Frame 6
7
R
R
IOM Frame 3
8th non-inverted "E" Bit
R
1
Application Notes
IOM Frame 7
IOM Frame 7
2
R
R
PEB 20550
PEF 20550
IOM Frame
R
3
ITD08108
01.96

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