PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 225

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CFI Synchronization Mode CMD1:CSM
The CFI interface can either be synchronized via the PFS pin (CMD1:CSS = 0), or via
the FSC pin (CMD1:CSS = 1). A transition from low to high of either PFS or FSC
synchronizes the CFI frame. The PFS (FSC) signal is internally sampled with the PDC
(DCL) clock:
If CSM is set to logical 0, the PFS/FSC signal is sampled with the falling clock edge of
PDC/DCL, if set to logical 1, the PFS/FSC signal is sampled with the rising clock edge
of PDC/DCL.
If CMD1:CSS is set to logical 0 (CFI clocks are internally derived from the PCM clocks),
then CMD1:CSM should be equal to PMOD:PSM.
If CMD1:CSS is set to logical 1 (CFI clock signals are inputs), then CMD1:CSM should
be selected such that stable low and high phases of the FSC signal can be detected,
meeting the set-up (
edge.
The high phase of the PFS/FSC pulse may be of arbitrary length, however it must be
assured that it is sampled low at least once before the next framing pulse.
The relationship between the framing and clock signals (PFS, FSC, PDC, DCL and RCL)
for the different modes of operation is illustrated in figures 68 and 69.
CFI Bit Number CMD2, CBNR:CBN9 … CBN0
The CFI data rate is determined by the reference clock RCL and the CFI mode selected
by CMD1:CMD1 … 0. The number of bits which constitute a CFI frame can be derived
from this data rate by division of 8000 (8 kHz frame structure). If the CFI interface is for
example operated at 2048 kBit/s, the frame would consists of 256 bits or 32 timeslots.
This number of bits must be programmed to CMD2,CBNR:CBN9 … 0 as indicated
below. Note that the formula is valid for all CFI modes:
CBN9 … 0 = number of bits – 1
Examples
A CFI frame consisting of 64 timeslots would require a setting of
CBN9 … 0 = 64 8 – 1 = 511D = 01 1111 1111
A CFI frame consisting of 48 timeslots would require a setting of
CBN9 … 0 = 48 8 – 1 = 383D = 01 0111 1111
Note: In case DCL and FSC are selected as inputs (CMD1:CSS = 1), FSC must always
Semiconductor Group
be synchronized with the positive edge of DCL (CMD1:CSM = 1). Otherwise, an
IOM-2 compatible timing cannot be installed by means of a bit shift (When the
negative edge is used for synchronization the internal frame start is delayed by
one DCL clock. In double rate mode a bit shift of half a bit cannot be adjusted).
Anyway, if the rising edges of DCL and FSC do not meet the frame setup time
T
FS
) and hold (
T
FH
) times with respect to the programmed DCL clock
225
B
B
Application Hints
PEB 20550
PEF 20550
01.96
T
FS
,