PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 328

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

STCR:
CTA2 … 0:
CTB2 … 0:
The SAXB register specifies for synchronous transfer channel B to which output
interface, port, and timeslot the serial data contained in the STDB register is sent.
ISXB:
MTXB6 … 0:
Synchronous Transfer Control
Register STCR
The STCR register bits are used to enable or disable the synchronous transfer utility and
to determine the sub-timeslot bandwidth and position if a PCM interface timeslot is
involved.
TAE, TBE:
Semiconductor Group
bit 7
TBE
Interface Select Transmit for channel B; selects the PCM interface
(ISXB = 0) or the CFI (ISXB = 1) as the output interface for
synchronous channel B.
timeslot number at the interface selected by ISXB according to
figure 84: MTXB6 … 0 = MA6 … 0.
Transfer Channel A (B) Enable; A logical 1 enables the P transfer, a
logical 0 disables the transfer of the corresponding channel.
Channel Type A (B); these bits determine the bandwidth of the
channel and the position of the relevant bits in the timeslot according
to tabel 50. Note that if a CFI timeslot is selected as receive or
transmit timeslot of the synchronous transfer, the 64 kBit/s bandwidth
must be selected (CT#2 … CT#0 = 001).
P Transfer Transmit Address for channel B; selects the port and
TAE
CTB2
CTB1
328
read/write reset value:
CTB0
CTA2
Application Hints
CTA1
undefined
PEB 20550
PEF 20550
bit 0
CTA0
01.96