PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 148

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CFI-mode 1
CFI-mode 2
CFI-mode 3
Table 20
Time Slot Encoding for Control Memory Accesses
CFI-mode 0
4.6.15 Memory Access Data Register (MADR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The Memory Access Data Register MADR contains the data to be transferred from or to
a memory location. The meaning and the structure of this data depends on the kind of
memory being accessed.
4.6.16 Synchronous Transfer Data Register (STDA)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The STDA-register buffers the data transferred over the synchronous transfer channel A.
MTDA7 to MTDA0 hold the bits 7 to 0 of the respective time slot. MTDA7 (MSB) is the
bit transmitted/received first, MTDA0 (LSB) the bit transmitted/received last over the
serial interface.
Semiconductor Group
bit 7
bit 7
MTDA7
MD7
MTDA6
MD6
H
H
MTDA5
MD5
bit U/D
bits MA6..MA3, MA0
bits MA2..MA1
bit U/D
bits MA6..MA3, MA2, MA0
bit MA1
bit U/D
bits MA6..MA0
bit U/D
bits MA6..MA4, MA0
bits MA3..MA1
Control Memory Address
MTDA4
MD4
148
MTDA3
MD3
read/write
read/write
read/write
read/write
Detailed Register Description
MTDA2
MD2
direction selection
time slot selection
logical CFI-port number
direction selection
time slot selection
logical CFI-port number
direction selection
time slot selection
direction selection
time slot selection
logical CFI-port number
address: 02
address: 03
address: 04
address: 06
MTDA1
MD1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
MTDA0
MD0
01.96