PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 184

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

RCS2..1
4.7.26 Transmit Channel Capacity Register (XCCR)
Access in demultiplexed P-interface mode:
XBC7..0
4.7.25 Time Slot Assignment Register Receive (TSAR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
TSNR5..0 Time Slot Number Receive.
Access in multiplexed P-interface mode:
Reset value: 00
Note: In extended transparent mode the width of the time slot has to be n
Semiconductor Group
bit 7
bit 7
TSNR5
XBC7
Selects one of up to 64 time slots (00
clock mode 2. The number of bits per time slot is programmable in register
RCCR.
Receive Clock Shift bit2-1.
Together with RCS0 in register CCR2 the transmit clock shift can be adjusted
in clock mode 2.
Transmit Bit Count.
Defines the number of bits to be transmitted in a time slot in clock mode 2
(number of bits per time slot = XBC + 1 (1…256 bits/time slot)).
TSNR4
XBC6
H
H
TSNR3
XBC5
TSNR2
XBC4
184
TSNR1
XBC3
write
write
write
write
H
- 3F
address: (Ch-A/Ch-B): 31
address: (Ch-A/Ch-B): 62
address: (Ch-A/Ch-B): 32
address: (Ch-A/Ch-B): 64
Detailed Register Description
TSNR0
H
XBC2
) in which data is received in
RCS2
XBC1
PEB 20550
PEF 20550
8 bits.
bit 0
bit 0
RCS1
XBC0
H
H
H
H
/71
/E2
/72
/E4
01.96
H
H
H
H