PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 116

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Read
Read
Read
Reset tristate field of Data Memory (DM)
Write
Write
Read
3.8.6.2 SACCO-A Initialization Example
Configure the SACCO-A for communication with downstream subscribers
Write
Write
Write
(Write
Write
Reset the SACCO-A’s FIFOs
Write
Read
Read
3.8.6.3 D-Channel Arbiter Initialization Example
Enable D-channel transmission to CFI-port 0, channel 0
(Write
Enable D-channel reception on CFI-port 0, channel 0
Write
Write
Set EPIC-1 to normal mode
Write
Semiconductor Group
ISTA = 20
ISTA_E = 08
MADR = 00
MACR = 68
STAR
MODE = A8
RAH1 = 00
RAH2 = 40
CCR2 = 00
CCR1 = 87
CMDR = C1
ISTA = 02
ISTA_A = 10
XDC = 00
AMO = F9
DCE0 = 01
OMDR = C0
STAR_E = 25
H
H
H
H
H
H
H
H
H
)
H
H
H
H
H
)
H
H
H
set EPIC-1 to CM-normal mode; Interrupt line will go active
EPIC-1 interrupt
PFI-interrupt: PCM-synchronisity status has changed
ELIC is synchronized to PCM-interface; MFIFO ready
all bits of time slot set to high impedance
write MADR to all locations of PCM-tristate field
Wait for STAR:MAC = 0
set SACCO-B to transparent mode 1; switch receiver active
response SAPI1: Signaling data
response SAPI 2: Packet-switched data
reset value: T DA pin disabled; standard data sampling;
RFS-interrupt disabled
power-up SACCO-A in point to point configuration and clock
mode 3 with double rate clock; inter frame timefill = all ’1’s
reset CPU accessible and CPU inaccessible part of RFIFO,
and reset XFIFO; the interrupt line will go active
interrupt of SACCO-A
transmit pool ready
reset value: broadcasting disabled; transmit to channel 0
of port 0
start with maximum selection delay; suspend counter active;
control of D-channel to take place via C/I-bit; control
channel master enabled
enable CFI-port 0, channel 0 for data reception
116
Operational Description
PEB 20550
PEF 20550
01.96