PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 83

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(6) The ASM-state changes from "receive frame" to "limited selection" when
(7) When the ASM detects a ’0’ on the serial input line it enters the state "expect
(8) When the ASM does not detect any ’0’ on the remaining serial input lines during n
(9) If n is set to 0, then the state “limited selection” is skipped.
The described combination of DCE and DCES implements a priority scheme
guaranteeing that (almost) simultaneous requesting subscribers are served sequentially
before one is selected a second time.
The current ASM-state is accessible in ASTATE7:5.
(5) When SACCO-A indicates the recognition of a frame (frame indication after
Semiconductor Group
receiving 3 bytes incl. the flag) before the suspend counter underflows the ASM
enters the state "receive frame".
SACCO-A indicates "end of frame". The receive strobe is turned off and the DCES-
bit related to the corresponding D-channel is reset. The ASM again monitors the
D-channels but limited to the group enabled in the slave registers DCES "anded"
with DCE. The "and" function guarantees, that the user controlled disabling of a
subscriber has immediate effect.
frame". Channel and port address of the related subscriber are latched in the
arbiter state register (ASTATE), the receive strobe for SACCO-A is generated and
the suspend counter is loaded with the value stored in register SCV. The counter is
decremented after every received byte. When simultaneously ’0’s are detected on
different IOM-2 channels, the lowest channel is selected.
IOM-frames (n is programmed in the register AMO) it re-enters the state "full
selection". The list of monitored D-channels is then increased to the group
selected in the user programmable DCE-registers. In order to avoid arbiter
locking n has to be greater than the value described in chapter 2.2.8.3 or must
be set to 0 (see chapter 4.8.1 Arbiter Mode Register).
83
Functional Description
PEB 20550
PEF 20550
01.96