PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 162

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.6.33 Version Number Status Register (VNSR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 0x
The VNSR-register bits do not generate interrupts and are not modified by reading
VNSR. The IR and VN3..0 bits are read only bits, the SWRX-bit is a write only bit.
IR
SWRX
VN3..0
Semiconductor Group
bit 7
IR
Initialization Request; this bit is set to logical 1 after an inappropriate clocking
or after a power failure. It is reset to logical 0 after a control memory reset
command: OMDR:OMS1..0 = 00, MACR = 7X.
Software Reset External.
When set, the pin RESIN is activated. RESIN is reset with the next EPIC-1
interrupt, i.e. the EPIC-1 timer may be used to generate a RESIN-pulse
without generating an internal ELIC-reset.
Version status Number; these bits display the EPIC-1 chip version as follows
VN3..0
0001
H
0
0
SWRX
162
VN3
Chip Versions
V1.2
write
write
Detailed Register Description
VN2
address: 3A
address: 1D
VN1
PEB 20550
PEF 20550
bit 0
H
H
VN0
01.96