PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 73

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PEB 20550
PEF 20550
Functional Description
Extended Transparent Mode 0 (MODE:MDS1, MDS0, ADM = 110)
Characteristics: fully transparent without HDLC framing, any message length, any
window size.
Data is stored in register RAL1.
In extended transparent mode, fully transparent data transmission/reception without
HDLC-framing is performed, i.e. without FLAG-generation/recognition, CRC-generation/
check, bit stuffing mechanism. This allows user specific protocol variations or can be
used for test purposes (e.g. to generate frames with wrong CRC-words).
Data transmission is always performed out of the XFIFO. Data reception is done via
register RAL1, which contains the actual data byte assembled at the RxD pin.
Extended Transparent Mode 1 (MODE:MDS1, MDS0, ADM = 111)
Characteristics: fully transparent without HDLC-framing, any message length, any
window size. Data is stored in register RAL1 and RFIFO.
Identical behavior as extended transparent mode 0 but the received data is shifted
additionally into the RFIFO.
Receive Data Flow (summary)
The following figure gives an overview of the management of the received HDLC-frames
depending on the selected operating mode.
Semiconductor Group
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