PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 153

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.6.24 MF-Channel Subscriber Address Register (MFSAR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The exchange of monitor data normally takes place with only one subscriber circuit at a
time. This register serves to point the MF-handler to that particular CFI time slot.
MFTC1..0
SAD5..0
CFI time slot encoding of MFSAR derived from MAAR:
MAAR:MA7 selects between upstream and downstream CM-blocks. This information is
not required since the transfer direction is defined by CMDR (transmit or receive).
MAAR:MA0 selects between even and odd time slots. This information is also not
required since MF-channels are always located on even time slots.
4.6.25 Monitor/Feature Control Channel FIFO (MFFIFO)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: empty
The 16-byte bi-directional MFFIFO provides intermediate storage for data bytes to be
transmitted or received over the monitor or feature control channel.
MFD7..0
Note: The byte n + 1 of an n-byte transmit message in monitor channel is not defined.
Semiconductor Group
MFSAR: MFTC1 MFTC0 SAD5 SAD4
bit 7
bit 7
MFTC1
MFD7
MF Data bits 7..0; MFD7 (MSB) is the first bit to be sent over the serial CFI,
MFD0 (LSB) the last.
MAAR:
MFTC0
MF Channel Transfer Control 1..0; these bits, in addition to CMDR:MFT1,0
and OMDR:MFPS control the MF-channel transfer as indicated in table 21.
Subscriber address 5..0; these bits define the addressed subscriber. The
CFI time slot encoding is similar to the one used for Control Memory
accesses using the MAAR-register (tables 19 and 20):
MFD6
H
MA7
MFD5
SAD5
MA6
MFD4
SAD4
MA5
153
MFD3
SAD3
SAD3
MA4
read/write
read/write
read/write
read/write
SAD2
Detailed Register Description
MA3
MFD2
SAD2
SAD1 SAD0
MA2
address: 0A
address: 14
address: 0B
address: 16
MFD1
SAD1
MA1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
MFD0
SAD0
MA0
01.96