PEF20550HV21XT Lantiq, PEF20550HV21XT Datasheet - Page 54

• Manufacturer Part Number: PEF20550HV21XT
• Manufacturer: Lantiq

Specifications of PEF20550HV21XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

local registers ISTA_A/B but remains stored internally and will be indicated again when
the corresponding MASK_A/B-bit is reset.
The SACCO-interrupt sources can be splitted in three logical groups:
• Receive interrupts
• Transmit interrupts
• Special condition interrupts
For further information refer to chapter 3.6.1 (Data Transmission in Interrupt Mode)
and chapter 3.6.3 (Data Reception in Interrupt Mode).
DMA-Interface
To support efficient data exchange between system memory and the FIFOs an
additional DMA-interface is provided. The FIFOs have separate DMA-request lines
(DRQRA/B for RFIFO, DRQTA/B for XFIFO) and a common DMA-acknowledge input.
The DMA-controller has to operate in the level triggered, demand transfer mode. If the
DMA-controller provides a DMA-acknowledge signal, each bus cycle implicitly selects
the top of FIFO and neither address nor chip select is evaluated. If no DACK signal is
supplied, normal read/write operations (providing addresses) must be performed
(memory to memory transfer).
The SACCO activates the DRQT/R-lines as long as data transfers are needed from/to
the specific FIFOs.
A special timing scheme is implemented to guarantee safe DMA-transfers regardless of
DMA-controller speed.
If in transmit direction a DMA-transfer of n bytes is necessary (n < 32 or the remainder
of a long message), the DRQT-pin is active up to the rising edge of WR of DMA-transfer
(n-1). If n
((k
there are further bytes to transfer (figure 27). When a fast DMA-controller is used
(> 16 MHz), byte n (or bytes k
the SACCO. In this case pin DRQT is not activated any more up to the next block transfer
(figure 26).
Interrupts
The SACCO indicates special events by issuing an interrupt request. The cause of a
request can be determined by reading the interrupt status register ISTA_A/B or EXIR_A/
B. The related register is flagged in the top level ISTA (refer to figure 46).
Three indications are available in ISTA_A/B, another five in the extended interrupt
register EXIR_A/B. An interrupt which is masked in the MASK_A/B is not indicated in the
top level register and the INT-line is not activated. The interrupt is also not visible in the
Semiconductor Group
32)
1). DRQT is activated again with the next rising edge of DACK (or CSS), if
32 the same behavior applies additionally to transfers 31, 63, …,
32) will be transferred before DRQT is deactivated from
(RFS, RPF, RME, EHC)
(XDU/EXE, RFO)
(XPR, XMR)
54
Functional Description
PEB 20550
PEF 20550
01.96