LSISASX12 LSI, LSISASX12 Datasheet
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... TECHNICAL MANUAL LSISASx12/LSISASx12A 3.0 Gbit/s Serial Attached SCSI / Serial ATA Expander Version 3.0 ® DB14-000277-04 ...
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... C standard Specification as defined by Philips. Document DB14-000277-04, Version 3.0, October 2005 This document describes LSI Logic Corporation’s LSISASx12/LSISASx12A 3.0 Gbit/s Serial Attached SCSI expander and will remain the official reference source for all revisions/releases of this product until rescinded by an update. ...
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... Preface This book is the primary reference and Technical Manual for the LSISASx12 and the LSISASx12A 3.0 Gbit/s Serial Attached SCSI (SAS) expander chips. It contains a complete functional description for the devices, as well as complete physical and electrical specifications. Audience This document assumes that you have some familiarity with computer chips and related support devices. The people who benefi ...
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... Chapter 5, mechanical specifications for the LSISASx12/LSISASx12A, as well as pinout diagrams for the LSISASx12/LSISASx12A. Appendix A, Register registers in the LSISASx12/LSISASx12A. Appendix B, Example Code for API2C Interface and Serial EEPROM, provides example code for programming the API2C interface to access a Serial EEPROM. Related Publications and Specifications ...
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... Final release version. Advance Version 0.2 12/2003 Initial release of document. Preface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Remarks Added LSISASx12A info and API2C registers and state machines. Updated “Related Publications and Added power dissipation footnote to Added Section 5.2, “ ...
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... Preface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... Routing 2.2.1 2.2.2 2.2.3 Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Single Expander Example Multiple Expander Example Path Redundancy Application Expander Features STP/SATA Features SMP Features Usability Flexibility Testing and Reliability Connection Manager and Router ...
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... SMP Target Registers 4.4 SPhynx Registers 4.4.1 4.4.2 viii Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Address Spaces SAS Addressing WRITE N REGISTERS (0xC0) READ N REGISTERS (0x40) GPIO/LED Configuration SIO Configuration SGPIO Pattern Generation Doorbell Interface ...
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... Write a 32-Byte Page to the Serial EEPROM B.3 Read a 32-Byte Page from the Serial EEPROM Index Customer Feedback Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Phy Configuration Registers Remote Bank Configuration Registers 4-99 4-124 4-124 4-129 ...
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... Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... Slave Write Operation 2.8 Slave Read Operation 3.1 LSISASx12 Signal Functional Grouping 5.1 Reset Input 5.2 LSISASx12 472-Pin BGA Top View 5.3 472-Pin EPBGA-T (UO) Mechanical Drawing (Sheet Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Slave Addressing and Transfer Modes 1-3 ...
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... Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... Connection Manager Remote Bank Register Map 4.15 I 5.1 Absolute Maximum Stress Ratings 5.2 Operating Conditions Version 3 and EMB Signal Description 2 C Slave Register Map Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. 2-8 2-12 2-13 2-15 2-15 2-16 2-19 2-27 2-27 2-34 3-4 ...
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... ECM Phy Register Map A.7 ECM Remote Bank Register Map A.8 ECM Remote Bank Register Map A.9 EMB Slave Register Map xiv Version 3.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-3 5-3 5-3 5-3 5-4 5-4 5-4 5-4 ...
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... Section 1.3, “Expander Communication” Section 1.4, “Features” 1.1 Overview The LSISASx12/LSISASx12A expander is a 12-port, 3 Gbit/s Serial Attached SCSI (SAS)/Serial ATA (SATA) expander device. The LSISASx12/LSISASx12A expander provides the functionality for connecting targets and initiators. The expander provides phys for SAS initiator, SAS target, SAS expander, or Serial ATA (SATA) target devices ...
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... LSI Logic SAS expanders are ideal for data centers and Storage Area Networks, leveraging existing SCSI infrastructure for investment protection and ease of migration and implementation the rest of this document LSISASx12 refers to both the LSISASx12 expander and the LSISASx12A expander unless specifically noted. 1-2 Introduction Copyright © ...
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... Application Examples The LSISASx12 can be used in simple topologies to attach an initiator to SAS/SATA devices, in edge expander topologies to increase the number of accessible devices fault-tolerant path-redundancy topologies to improve system reliability. By cascading multiple LSISASx12 expanders, users can attach up to 144 devices. The LSISASx12 expander can be used to construct many different SAS topologies ...
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... Multiple Expander Example To increase the number of devices within a topology, multiple LSISASx12 expanders can be cascaded into edge expander device sets as illustrated in external support components including a reference clock and a Serial EEPROM device. A single serial EEPROM can provide unique configurations four LSISASx12 expanders. ...
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... LSISASx12 provides an SMP block that enables initiator devices to communicate directly to the LSISASx12. The SMP Target provides access to the standard SMP functions and extended functions of the LSISASx12. Initiators can use the SMP Target to perform discovery on the LSISASx12 expander. Expander Communication Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... SATA Port Selector Report Manufacturing Information in the format defined by the SAS version 1.1 specification BREAK handling clarifications ALIGH transmission from expanders 1.5 Gbits/s and 3.0 Gbits/s SAS 1.5 Gbits/s and 3.0 Gbits/s SATA (on LSISASx12A only bus to the STP target enclosure ...
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... STP/SATA Features This subsection describes the STP features. The LSISASx12 supports SATA data transfers of 1.5 Gbits/s The LSISASx12A supports SATA data transfers of 1.5 Gbits/s or 3.0 Gbits/s Supports STP data transfers of 3.0 Gbits/s and 1.5 Gbits/s Allows addressing of multiple SATA targets Allows multiple initiators to address a single target 1 ...
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... LSISASx12 expander. Allows concurrent connections to SAS or SATA targets Offers configurable options – – – Allows flexible allocation of routing table entries to the LSISASx12 phys Allows reuse of routing table resources across all of the phys composing a wideport 1.4.6 Testing and Reliability This subsection describes the testing and reliability features. ...
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... Chapter 2 Functional Description This chapter provides a subsystem level overview of the LSISASx12 expander chip. This chapter consists of the following sections. Section 2.1, “Block Diagram Description” Section 2.2, “Routing” Section 2.3, “Addressing” Section 2.4, “Vendor-Specific SMP Application Layer Commands” ...
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... Figure 2.1 LSISASx12 Block Diagram SMP Target TX[0] SPhynx[0] RX[0] TX[1] SPhynx[1] RX[1] TX[2] SPhynx[2] RX[2] TX[3] SPhynx[3] RX[3] TX[4] SPhynx[4] RX[4] TX[5] SPhynx[5] RX[5] UART_TX Serial UART_RX Debugger 2-2 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... Registers,” illustrates the operation of the connection manager. Figure 2.2 Link 0 Link Block Diagram Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Section 4.2, “Configuration Manager describe the connection manager registers. Connection Manager and Router Operation Arbitration Interface ...
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... SPhynx[0] to SPhynx[11]. These modules are also referred to as Phy[0] to Phy[11]. 2.1.3 SMP Target The SMP target supports SMP functions on the LSISASx12 expander. This block decodes SMP packets destined to the expander device and performs the requested operation. The SMP target also provides generation of SMP response frames. ...
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... The STP target enclosure management bridge (STP EMB STP bridge that allows communication with an enclosure management processor. This block transports STP packets between the LSISASx12 expander and the optional external enclosure management processor. The STP EMB supports connection management to the external enclosure management processor, consisting of doorbell communication and data transfer functions ...
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... The use of the ISTWI_ADDR[1:0] signals permits a single serial EEPROM to provide boot records for up to four LSISASx12 expanders. Loader, Serial EEPROM, and API2C Interface,” on page 2-17 more information on the boot sequencer, boot record, and serial EEPROM loader ...
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... Siolkout, SioDout, SioStart, SioEnd, and SioDin signals. SioStart and SioEnd control the input and output data streams, SioDout and SioDin. The SIO signals are mapped to the LSISASx12 GPIO/LED signals. The LSISASx12A provides enhanced SGPIO support which is not available on the LSISASx12. The enhanced functionality enables additional data modulation for blink rates and blink patterns ...
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... SioDin line. In Single originator mode, which is set by the SioMode bit in the SIO Control register, the SioEnd signal provides the start signal, and the LSISASx12 does not require an SioStart input. O This signal provides the serial data output line. ...
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... The spin-up controller. The LSISASx12 uses the Spin Mode parameter to provide special spin-up support for phys that are connected to SATA drives. The Immediate mode allows OOB to occur with the drive as soon as both phys are ready ...
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... Table Routing The LSISASx12 supports 144 routing table entries in 12 banks with 12 entries each. Each phy can be configured to use any or all of the 12 banks, provided that the banks are contiguous. All entries include the WWN and a disable bit ...
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... These registers are described in Slave Registers,” on page 2.3.2 SAS Addressing Each LSISASx12 expander requires a block of 16 addresses starting at 0x000–0xFFFF. When performing STP-SATA Bridge addressing or Addressing Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Section 4.6, “Expander Connection Manager Registers,” on registers ...
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... World Wide Name bits [63:4], and address bits [3:0] are given by the port number bits [3:0]. LSISASx12. Table 2.2 Port 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC ...
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... Descriptions of these fields follow. StartAdr[18:3] specifies the starting 8-byte boundary to begin the register write operation. Vendor-Specific SMP Application Layer Commands Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. N 127 and N specifies the number of 8-byte register write Table 2.3 ...
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... If 0 < N <128 and the size of the Request Frame is not (N dwords, the function result is set to 0xh03 (INVALID REQUEST FRAME LENGTH) and no registers are written. 2-14 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. shows the response frame format. The response conditions 8]. This allows for ...
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... Table 2.5 Byte – Vendor-Specific SMP Application Layer Commands Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved SMP FRAME TYPE (0x41) Function (0xC0) Function Result Reserved (MSB) CRC N 127 and N specifies the number of 8-byte Table 2.5 shows the format for the READ N ...
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... The following describes the Read Response frame fields. 2-16 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. provides the response frame format. The response conditions SMP Frame Type (0x41) Function Result (0x00 or 0x02) ...
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... Boots are retried up to seven times if errors occur. If the boot ultimately fails then the phys are disabled and the LSISASx12 generates an interrupt to the Enclosure Processor. The optional data field can configure GPIO/LEDs, nonstandard time-outs, or any register that this document describes. The confi ...
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... Address 1 Base Vector lSTWI Address 2 Base Vector lSTWI Address 3Base Vector 2-18 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. shows the format of the boot record. The data fields in the Boot Record Format 0x00 0x01 0x02 ...
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... CfgMgr CfgMgr CfgMgr CfgMgr 0x00014 CfgMgr CfgMgr CfgMgr Boot Loader, Serial EEPROM, and API2C Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. shows the contents of the fixed data field within the boot Offset 0 Safety Byte 1 WWN Base Address 2 3 ...
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... CfgMgr 0x00020 CfgMgr CfgMgr CfgMgr 0x00040 CfgMgr CfgMgr CfgMgr CfgMgr 0x00044 CfgMgr CfgMgr CfgMgr CfgMgr 0x00048 CfgMgr CfgMgr CfgMgr 2-20 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Offset 25 Product ID (cont Product ID (cont Product Revision Spin-up Control 37 ...
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... Phy (all) Phy (all) ECM 0x60000 ECM 0x60004 ECM ECM 0x60010 ECM 0x60014 ECM ECM 0x60020 ECM 0x60024 ECM Boot Loader, Serial EEPROM, and API2C Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Offset 48 TX/RX Polarity GigaBlaze RX Confi GigaBlaze TX Confi ...
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... ECM ECM 0x60090 ECM 0x60094 ECM ECM 0x600A0 ECM 0x600A4 ECM ECM 0x600B0 ECM 0x600B4 ECM 2-22 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Offset 77 Expander Connection 78 Manager Registers 79 Configuration (cont Expander Connection 87 Manager Registers 88 Confi ...
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... GPIO/LED and SIO Configuration This section describes the use and configuration of the GPIO, LED, and SIO signals. GPIO/LED and SIO Configuration Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Offset 104 Route Table Configuration ...
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... GPIO/LED Configuration The LSISASx12 provides a total of 52 LED and GPIO signals. There are four GPIO signals (GPIO[3:0]) and 48 LED signals (LED_ACTIVITY[11:0]/, LED_FAULT[11:0]/, LED_STATUS[11:0]/, and CABLE_DET[11:0]/). The LED signals are associated with the SAS ports on the device, but can also be used as GPIO signals. The configuration manager LED control registers can confi ...
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... Figure 2.4 LSISASx12 GPIO/LED Control Structure GPIO Control Register GPIO Value Register Activity Fault Combo Inverted Activity (Only GPIO available for Group 0) LED Group Control Register (Selectable on a per Group Basis) LED Blinker 1 Register LED Blinker 2 Register LED Blinker 3 Register Group Override Register (Selectable on a per Bit Basis) Figure 2 ...
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... LED blink patterns between multiple LSISASx12 devices. The LEDSYNCOUT pin emits a 0.5 Hz square wave, which can be applied to the LEDSYNCIN pin on other LSISASx12 devices to synchronize blinker patterns on the devices. Each blinker definition has the ability to override the blink pattern and use the 0.5 Hz LEDSYNCOUT signal to drive the signals that the blinker defi ...
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... LSISASx12A expander in the enhanced SGPIO mode. the encoding of the SIO Control Select bit. Table 2.8 SIO Control Select 0 1 2.6.3 SGPIO Pattern Generation This section describes how to program the enhanced SGPIO interface on the LSISASx12A expander. There are four programmable pattern definition registers that define the LED blink pattern (SIO Pattern Defi ...
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... Receiving SATA Frame Information Structures (FIS). Checking CRC on inbound SATA FIS. 2-28 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Program the Pattern Definition 0 register to 0b00000111110000011111. Set the SIO Control Select bit in the to 0b1 to enable the enhanced SGPIO interface. ...
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... Generating interrupts to the external SEP when commands and data are available for the SEP to process. Generating and transmitting SATA FISes (D2H Register, PIO Setup, and Data FISes). STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. 2-29 ...
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... Doorbell Interface The STP EMB doorbell messaging interface provides a communication channel between the STP target and the SEP. The LSISASx12 STP sets the various bits in the STP-SEP Doorbell registers to send commands to the SEP. The STP-SEP Doorbells are the interrupt sources. ...
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... Device users can enable or disable CRC checking by writing to the Error Detection Control register. If CRC checking is disabled, then the LSISASx12 still transmits CRC bytes during data transfers. CRC checking is enabled by default after reset. When CRC checking is STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... CRC. The header CRC covers the address and the byte count; the payload CRC covers the data. The fourth byte of the transfer contains the header CRC. If the LSISASx12 detects an error in the address or byte count, it asserts the EMB_CRC_INT signal. The data transfer can continue, but the LSISASx12 discards the data ...
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... ATAPI Command Status Table 2.10 These commands allow the EMB to access a bridge and to operate with an ATAPI host. STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. 2 illustrates I C read operations. For byte read transfers, the Byte Read ...
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... READ SECTOR None (0x20) IDENTIFY None DEVICE (0xEC) 2-34 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes None None None None None None None ...
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... Error) SepDbell[ EXEC DEV StpDbell[ DIAGNOSTICS (RST_CMD_RCVD) (0x90) (SEP Diag. Error) SepDbell[ STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes None None None StpDbell[ CmdStatus = 0x01 ...
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... SepDbell[ PACKET (A0h) None (w/ Features[DMA PACKET (A0h) None (w/ Features[OVL 2-36 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes None StpDbell[ CmdStatus = 0x00 SepDbell[ (STATUS_RDY) None StpDbell[ CmdStatus = 0x01 ...
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... Ready (00h) (MaxByteCnt > StpDbell[ 16’d1024) (PCKT_CMD_RCVD) Note: MaxByteCnt[15:0] = {CylinderHi, CylinderLo} SepDbell[ STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes (CDB Transfer (Data-Out IStatus[BSY IStatus[DRDY StpDbell[ ...
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... Xfer Length = 1 Kbyte StpDbell[ (PCKT_CMD_RCVD) (MaxByteCnt > 16’d1024) SepDbell[ StpDbell[ (WRITE_DATA_RCVD) SepDbell[ SepDbell[ 2-38 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes (CDB Transfer (Data-Out IStatus[BSY IStatus[DRDY StpDbell[ ...
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... SepDbell[ StpDbell[ (WRITE_DATA_RCVD) SepDbell[ StpDbell[ (WRITE_DATA_RCVD) SepDbell[ SepDbell[ STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes (CDB Transfer (Data-Out IStatus[BSY StpDbell[ IStatus[DRDY ...
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... Diagnostic Results (0x1C) StpDbell[ Xfer Length = 1 (PCKT_CMD_RCVD) Kbyte (MaxByteCnt > 16’d1024) SepDbell[ StpDbell[ (RD_DATA_XMITTED) 2-40 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes (CDB Transfer (Data-Out IStatus[BSY StpDbell[ IStatus[DRDY ...
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... Xfer Length = 1.5 (PCKT_CMD_RCVD) Kbytes (MaxByteCnt > 16’d1024) SepDbell[ StpDbell[ (RD_DATA_XMITTED) SepDbell[ StpDbell[ (RD_DATA_XMITTED) STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes (CDB Transfer (Data-Out IStatus[BSY IStatus[DRDY ...
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... Sense (0x03) Xfer Length = 20 StpDbell[ bytes (PCKT_CMD_RCVD) (MaxByteCnt > 16’d1024) SepDbell[ StpDbell[ (RD_DATA_XMITTED) 2-42 Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes (CDB Transfer (Data-Out IStatus[BSY StpDbell[ IStatus[DRDY ...
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... Xfer Length = 800 StpDbell[ bytes (PCKT_CMD_RCVD) (MaxByteCnt = 16’d512) SepDbell[ StpDbell[ (RD_DATA_XMITTED) SepDbell[ StpDbell[ (RD_DATA_XMITTED) STP Enclosure Management Interface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expected SEP Expected SATA Doorbell Writes PIO Setup FISes (CDB Transfer (Data-Out IStatus[BSY IStatus[DRDY StpDbell[ ...
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... Functional Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... Chapter 3 Signal Descriptions This chapter describes the LSISASx12 expander signals and consists of the following sections. Section 3.1, “Signal Types” Section 3.2, “Functional Signal Grouping” Section 3.3, “SAS/SATA Signals” Section 3.4, “Serial EEPROM Signals” 2 Section 3.5, “I C and EMB Signals” ...
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... P G 3.2 Functional Signal Grouping Figure 3.1 3-2 Signal Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Input, a standard input-only signal Output, a standard output driver Input and output (bidirectional) Power Ground contains the functional signal groupings of the LSISASx12. ...
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... LED_FAULT[11:0]/ LED_STATUS[11:0]/ LEDSYNC_OUT 1. The SIO signals are multiplexed and do not appear in tiplexed SIO Interface,” on page 3-7 Functional Signal Grouping Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. LSISASx12 Signal Functional Grouping RTRIM REFCLK TX[11:0] SAS/SATA Interface RX[11:0] BSL_SCL ...
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... SAS/SATA signals. Description I The Reference Clock signal provides the serial differential clock to the LSISASx12 expander. Connect a 75 MHz oscillator having an accuracy of at least 50 ppm to these pins. To use a single-ended oscillator, REFCLK+ and REFCLK must be driven through a single-ended to differential level-shifting network. ...
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... Provides the block offset of the configuration data in the serial EEPROM memory to the boot strap loader. This structure enables a single serial EEPROM to contain separate configuration data for up to four LSISASx12 expanders 3-5 ...
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... Power-On-Reset (POR) state. I The Clock pin provides 75 MHz clock for the internal control logic. Refer to SEN S11054: LSISASx12 Design Considerations (DB05-000116-xx) for information concerning this signal. I/O The General Purpose Input/Output (GPIO) pins provide general purpose inputs and/or outputs. ...
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... SioDout line during the next clock cycle, and that data can be received on the SioDin line. In Single originator mode, which is set by the SioMode bit in the SIO Control register, the SioEnd signal provides the start signal, and the LSISASx12 does not require an SioStart input. AF18 O This signal provides the serial data output line ...
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... Table 3.5 Multiplexed SIO Signals (Cont.) LSISASx12 Signal SIO Signal LED_STATUS[10]/ SioClkin LED_STATUS[11]/ SioClkout LEDSYNCOUT BlinkClkin LEDSYNCIN BlinkClkout AF15 3.8 JTAG Pins Table 3.6 Table 3.6 Signal Name BGA Position I/O Description TCK TRST/ TDI TDO TMS 3.9 Factory Test Pins Table 3 ...
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... VDD2 M13, M15, U4, AA3, AB5, Y3, K23, L24, M24, N12, N14, P13, P15, R12, R14, R3, T3 Power and Ground Pins Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Type Description I Used for LSI Logic production test only. I Used for LSI Logic production test only. ...
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... W20 TX_VDD[11:0] AD2, AB2, V2, P5, J3, E3, D26, H25, P26, R23, AA24, AE25 3-10 Signal Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Type Description Ground VSS2 Ground. These pins provide Core and I/O ground. Power PLL_VDD Power. These pins provide 1 ...
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... AE14, AF8, AF10, AF11, AF12, AF13, AF14 Power and Ground Pins Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Type Description Ground TX_VSS supplies ground for transmitter analog section of each GigaBlaze core. No connect. These signals do not connect inside of the LSISASx12 package. 3-11 ...
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... Signal Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
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... Chapter 4 Register Descriptions This chapter provides the address map and register descriptions for the LSISASx12 expander chip. This chapter contains the following sections: Section 4.1, “Primary Internal Registers Address Map” Section 4.2, “Configuration Manager Registers” Section 4.3, “SMP Target Registers” ...
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... Phy Registers SPhynx[11] Link Registers SPhynx[11] Phy Registers STP Target Registers 4-2 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. provides a top-level address map for the LSISASx12. Each Size 64 Kbytes 32 Kbytes 32 Kbytes 128 Kbytes 1 Kbyte 1 Kbyte 1 Kbyte ...
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... Kbytes provides the register map for the Configuration Manager Config Configuration Manager Config Register Map LSISASx12 Expander SAS Address High LSISASx12 Expander SAS Address Low Vendor Identifier High Vendor Identifier Low Component Vendor ID High Component Vendor ID Low Component ID and Revision Vendor Specifi ...
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... Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Configuration Manager Config Register Map (Cont.) Register Name Phy Receiver Polarity Boot Control and Status API2C Global Control API2C Interrupt Status ...
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... Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Register Name Reserved LED Group Control Group 0 GPIO Control Group 1 GPIO Control Group 2 GPIO Control Group 3 GPIO Control Group 4 GPIO Control ...
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... LSISASx12 SAS Address High WWN High This field provides World Wide Name (WWN) bits [63:32]. The boot loader writes this value during initialization. The LSISASx12 copies this value to the SMP target, STP tar- get, and each SPhynx module LSISASx12 SAS Address Low ...
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... Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. WWN Low This field provides WWN bits [31:0]. The boot loader writes this value during initialization. The LSISASx12 copies this value to the SMP target, STP target, and each SPhynx module. Set the least significant nibble of this register to 0xF ...
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... ASCII text string. The boot loader writes this field during initialization. Set the lower nibble of this register to 0xF Product ID 3 (on LSISASx12 Vendor Identifier High (on LSISASx12A) Product ID 3 This field provides Product Identifier bits [127:96]. The boot loader writes this field during initialization ...
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... This field contains Product Identifier bits [95:64]. The boot loader writes this field during initialization Product ID 1 (on LSISASx12 Vendor Identifier High (on LSISASx12A) Product ID 1 This field contains Product Identifier [63:32]. The boot loader writes this field during initialization ...
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... Load this field with the ASCII bytes representing the revi- sion level of the subsystem (board or enclosure) contain- ing this expander device. The upper three bytes are loaded by the Boot Sequencer as part of the fixed record. On the LSISASx12 the lowest bytes defaults to 0x20 ...
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... Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. indicate an ASCII space, but may also be loaded by the Boot Sequencer with an optional write. Left-align data within this field. On the LSISASx12A all bytes default to 0x20202020 Component Vendor ID High Component Vendor ID High This read-only fi ...
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... Component ID This field contains Component ID. This field is hardwired to 0x0200 on the LSISASx12 and hardwired to 0x0205 on the LSISASx12A. Revision ID This field contains the revision ID. This field is hardwired to 0x01 on the LSISASx12 and to 0x00 on the LSISASx12A. Reserved 16 15 Vendor Specific Dword Vendor Specific Dword 1 This fi ...
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... Register: 0x003C Read/Write Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. This field contains Vendor Specific Dword 0. The boot loader optionally writes this field during initialization Report General Expander Change Count This read-only field provides the count of the BROADCAST(CHANGE) primitive sequences that this device initiated. The value in this fi ...
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... This field indicates the spin-up delay in milliseconds. Reserved Spin Number This field specifies the maximum number of phys that the LSISASx12 is permitted to concurrently spin up. Reserved Spin Mode This field specifies the spin-up mode for phys that are attached to SATA devices. The encoding of this field is: Bit Value Defi ...
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... Register: 0x004C Read/Write Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Phy Configuration Reserved SMP Target Enable Setting this bit enables the SMP Target within the expander. The boot loader writes this field during initial- ization. The value of this fi ...
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... Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. This field contains the transmit polarity bits for each phy. Setting a bit inverts transmitter polarity for the corre- sponding phy from the default polarity of the phy. This is done to improve routing of board designs. Bit [0] corre- sponds to Phy[0], while bit [11] corresponds to Phy [11] ...
Page 95
... This register independently enables the master unit and globally enables and disables the IBML time-out timers Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ISTWI Address This read-only field provides the value of the ISTWI address input pins. This is also referred to as the I address. Reserved ...
Page 96
... Read/Write This register reports the status of the master state machine interrupt sources 4-18 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Master Enable This bit enables the API2C master state machine. API2C Master State ME Machine 0 Disable 1 Enable ...
Page 97
... This register controls the wait timer. The wait timer times API2C transactions and causes the appropriate state machine to take action when a time-out occurs. R Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Interrupt Enable register bit and through the external interrupt Reserved These bits are reserved ...
Page 98
... This register controls the API2C t time that the SCL signal is detected LOW. 4-20 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Timer Enable This bit enables the wait timer. TE Function 0 Disables the timer and forces time-out fl ...
Page 99
... SCL signal LOW during the transmission or reception of a data byte. R Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Reserved These bits are reserved. Timer Enable This bit enables the API2C t ...
Page 100
... The value in the register picks a power of two value from a free running 16-bit counter that serves as an enable for the timers. R 4-22 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Timer Enable This bit enables the API2C t TE Function ...
Page 101
... SDAE SCLE SDAC Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Divider Select This field selects the bit position from a 16-bit counter to use as an enable for the timers. Bit 3 is the most signifi- cant bit (MSB). ...
Page 102
... This register allows the host to independently reset the API2C interface. R I2CR 4-24 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. SCL Control This bit controls the SCL signal. SCLC Function 0 SCL is not forced LOW. 1 SCL is forced LOW on the API2C interface ...
Page 103
... This register issues commands to the master state machine Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Flushes (reset pointers) the Transmit and Receive FIFOs 16 15 API2C Master Command Reserved These bits are reserved. Send Command When software sets this bit, the master state machine issues the command that the command type fi ...
Page 104
... The API2C core ignores writes to this register during the execution of a data transfer command. R RXTL 4-26 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Receive Transfer Length Reserved These bits are reserved. Receive Transfer Length This fi ...
Page 105
... The API2C core ignores writes to this register during the execution of a data transfer command. R TXTL Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Transmit Transfer Length Reserved These bits are reserved. Transmit Transfer Length This fi ...
Page 106
... This Address Register 1 (AR1) is sent as the first byte in the address phase of an API2C transaction. R I2CA1 AD 4-28 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Address Register 1 Reserved These bits are reserved. API2C Address 1 These bits are sent as the first seven bits of the address phase in an API2C transaction ...
Page 107
... A write to this register places data into the Transmit FIFO. A read to this register retrieves data from the top of the Receive FIFO. R MDP Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Address Register 2 Reserved These bits are reserved. ...
Page 108
... FIFO. R 4-30 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. A read to this location returns the data from the Receive FIFO at the read pointer location and then increments the read pointer. If the Receive FIFO is empty, the data pointed to by the read pointer is returned, but the read pointer is not incriminated ...
Page 109
... R MIE R Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Receive FIFO Depth This field indicates the current number of data bytes in the Receive FIFO. A value of 0 means the Receive FIFO is empty, while a value of 8 indicates the Receive FIFO is full ...
Page 110
... API2C signals an interrupt when one or more of these bits are set RFL 4-32 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Master Interrupt Status Reserved These bits are reserved. API2C T TIMEOUT This bit sets the T TIMEOUT master controller is in control of the API2C interface ...
Page 111
... Transmit FIFO is empty and transmit transfer length has not been met the Receive FIFO is full and receive transfer length has not been met Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved ...
Page 112
... STP TTP Note: 4-34 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. This bit clears when it is read or when a new command is issued. Arbitration Lost This bit sets any data transfer command loses API2C interface arbitration. This bit clears to 0 when it is read or when a new command is issued ...
Page 113
... This register tracks the number of successfully transmitted (acknowledged) data bytes. R NBT Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Receive Transfer in Process When this bit is set, it indicates that the master state machine is processing the receive (read) part of a data transfer. ...
Page 114
... This register determines the high period for the SCL clock generated by API2C master state machine. The value specifies the number of PCLK cycles that the SCL clock is HIGH. 4-36 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Receive Bytes Transferred Reserved These bits are reserved. ...
Page 115
... PCLK cycle. When the counter reaches 0, the SCL state machine transitions to the master wait state and releases the SCL signal. R Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Reserved These bits are reserved. SCL High Clock Count This value loads in the 16-bit SCL timer ...
Page 116
... R FS 4-38 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. SCL Low Clock Count This is the value loads in the 16-bit SCL timer. Program an appropriate value for the desired speed mode. The available modes are the standard mode or the fast mode ...
Page 117
... SDA. The programmed value specifies the length of time that SDA is stable prior to a rising edge on SCL. This value is in units of PCLK cycles. Note: R SDASC Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C Setup Time This register provides the t SU:DAT API2C interface. Reserved These bits are reserved ...
Page 118
... SDA signal is stable following a falling edge on SCL. This value is in units of PCLK cycles. Note: R SDAHC 4-40 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved API2C SDA Hold Time This register provides the t HD:DAT API2C interface. Reserved These bits are reserved ...
Page 119
... The Inverted Activity setting asserts the LED in the same manner as the Activity Activity setting case, except that the polarity is inverted. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved LED Group Control Table 4.3. Settings other than those defined in this table medium blink rate when waiting for permission to spin up fast blink rate between OOB and fi ...
Page 120
... Register: 0x8004 Read/Write 4-42 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. This field provides configuration for the LED_ACTIVE[11:0]/ signals. Group 1 Configuration This field provides configuration for the CBL_DET[11:0]/ signals. Group 0 Configuration This field provides configuration for the GPIO[3:0] signals. ...
Page 121
... Register: 0x800C Read/Write Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 1 GPIO Control Reserved GPIO Direction If the Group 1 configuration is set to GPIO, then this field controls the direction of the pin in the Group 1 pinset. Setting the associated bit configures the pin as an output. ...
Page 122
... Register: 0x8014 Read/Write 4-44 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 3 GPIO Control Reserved GPIO Direction If the Group 3 configuration is set to GPIO, then this field controls the direction of the pin in the Group 3 pinset. Setting the associated bit configures the pin as an output. ...
Page 123
... Register: 0x801C Read/Write Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 0 GPIO Value Reserved GPIO Value If the Group 0 configuration is set to GPIO, then these bits control or observe the state of the associated pin. A write of this register sets the output value, and a read of this register returns the input value. If the pin is confi ...
Page 124
... Register: 0x8024 Read/Write 4-46 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 2 GPIO Value Reserved GPIO Value If the Group 2 configuration is set to GPIO, then these bits control or observe the state of the associated pin. A write of this register sets the output value, and a read of this register returns the input value. If the pin is confi ...
Page 125
... Group Configuration is not set to GPIO. The default for this register is approximately a 1/3 s pulse. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 4 GPIO Value Reserved GPIO Value If the Group 4 confi ...
Page 126
... Configuration is not set to GPIO. The default for this register is approximately pulse. 4-48 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Use LEDSYNC_OUT Pin Setting this bit causes the blink generator to ignore the Time Base and Pattern fields, and to source its output from the LEDSYNC_OUT pin ...
Page 127
... Group Configuration is not set to GPIO. The default for this register is intermittent blinking, approximately 1/5 s every 2 s. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved LED Blinker Definition 3 Time Base This fi ...
Page 128
... Value 0x00 0x01 0x02 0x03 4-50 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 0 Override Table 4.4. Note the transition to or from a Group Override Pin Operation Function No override. The pin functions according to their group configuration. ...
Page 129
... The pattern is not completed when transitioning out. The pattern starts where it last was in its rotation when transitioning in. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 1 Override Table 4.4. Note the transition to or from a ...
Page 130
... The pattern is not completed when transitioning out. The pattern starts where it last was in its rotation when transitioning in. 4-52 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 2 Override Table 4.4. Note the transition to or from a ...
Page 131
... The pattern is not completed when transitioning out. The pattern starts where it last was in its rotation when transitioning in. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 3Override Table 4.4. Note the transition to or from a ...
Page 132
... The pattern is not completed when transitioning out. The pattern starts where it last was in its rotation when transitioning in. 4-54 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Group 4 Override Table 4.4. Note the transition to or from a ...
Page 133
... This SIO module participates in the generation of an SIO output data stream as an originator. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved SIO Configuration When bit 0 of this register is set, the value in this field is the mux control code that is transmitted on the SioEnd line after setting the Transmit Mux Control bit. Encodings for the value in this register are receiver defi ...
Page 134
... Equation 4.1 4-56 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. The first input bit of the receive cycle must be ignored. Do not set this field to a value less than 2 when SIO Mode is set SIO Run Enable This bit enables transmit and receive operations on the SIO interface ...
Page 135
... Read/Write Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. SIO Enable Setting this bit selects SIO functionality for the SIO pins. SIO Mode This bit indicates the SIO mode. Clearing this bit config- ures the SIO for a single participant. Setting this bit con- fi ...
Page 136
... Register: 0xC00C Read/Write 4-58 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved SIO Receive 1 Reserved SIO Receive 1 When the SIO Device Count is set 11, bit 0 of this register contains bit 32 from the SioDin line and bits [3:1] of this register are reserved. When SIO Device Count is set to 11, bits [3:0] of this register contain bits [35:32] from the SioDin line ...
Page 137
... SGPIO mode; the other bit field definition provides the bit definitions for the enhanced SGPIO mode only available on the LSISASx12A. Each byte of this register generates 3 serialized I/O bits on the SioDout line. This register controls SIO bits [11:0], which are for devices 3 through 0. The following are the bit defi ...
Page 138
... The following are the bit definitions for enhanced SIO mode: 4-60 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. SIO bit 10: Locate Device 3 SIO bit 9: Active Device 3 SIO bit 8: Error Device 2 SIO bit 7: Locate Device 2 SIO bit 6: Active Device 2 ...
Page 139
... OFF 0b110 Inverted Blink (500 ms OFF, 500 ms ON) 0b111 Inverted Blink at Hz (250 ms OFF, 250 ms ON) Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. SIO Adapter Control Definition OFF ON Blink (500 ms ON, 500 ms OFF) Blink at Hz (250 ms ON, 250 ms OFF) ...
Page 140
... When the SIO Control Select bit in the 0xC054 encodings are: 4-62 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. is set, the enhanced SGPIO mode is enabled and the bit Active Field Encoding Definition 0b00 OFF ob01 ON 0b10 Activity ...
Page 141
... SGPIO mode; the other bit field definition provides the bit definitions for the enhanced SGPIO mode only available on the LSISASx12A. Each byte of this register generates 3 serialized I/O bits on the SioDout line. This register controls SIO bits [23:12], which are for devices 7 through 4. See the encoding for Error, Active, and Locate bits above as defi ...
Page 142
... One bit field definition provides the bit definitions for the standard SGPIO mode; the other bit field definition provides the bit definitions for the enhanced SGPIO mode only available on the LSISASx12A. 4-64 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...
Page 143
... SIO bit 10: Locate Device 11 SIO bit 9: Active Device 11 SIO bit 8: Error Device 10 SIO bit 7: Locate Device 10 SIO bit 6: Active Device 10 SIO bit 5: Error Device 9 Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. [31:29] [28:27] [26:24] [23:21] [20:19] [18:16] ...
Page 144
... Register: 0xC024 Read/Write 4-66 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. SIO bit 4: Locate Device 9 SIO bit 3: Active Device 9 SIO bit 2: Error Device 8 SIO bit 1: Locate Device 8 SIO bit 0: Active Device SIO General Purpose Output Data 0 General Purpose Output Data [31:0] These bits are transmitted bit for bit ...
Page 145
... R/W Register: 0xC044 Read/Write This register controls the enhanced SGPIO pattern definition on the LSISASx12A expander. This register is not present on the LSISASx12 expander. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved SIO Pattern Definition 0 Timebase 0 Clearing this bit causes the pattern to rotate at 40 Hz, which provides an interval between each bit shift ...
Page 146
... Read/Write This register controls the enhanced SGPIO pattern definition on the LSISASx12A expander. This register is not present on the LSISASx12 expander. 4-68 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. shift. Setting this bit causes the pattern to rotate at 10 Hz, which provides an interval of 100 ms between each bit shift ...
Page 147
... Register: 0xC050 Read/Write This register controls the enhanced SGPIO pattern definition on the LSISASx12A expander. This register is not present on the LSISASx12 expander. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved SIO Pattern Definition 3 Timebase 3 Clearing this bit causes the pattern to rotate at 40 Hz, which provides an interval between each bit shift ...
Page 148
... Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Minimum Deassert Time This field provides the minimum amount of time to deas- sert a Link Active signal. The default setting of this field is 0b0000, indicating 1/64 seconds. The encoding for this fi ...
Page 149
... Read/Write This register controls the enhanced SGPIO pattern definition on the LSISASx12A expander. This register is not present on the LSISASx12 expander. Configuration Manager Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Force Off Amount of time to deassert a Link Active signal in units of 1/8 seconds following a maximum assertion time. This fi ...
Page 150
... SMP target register map. Detailed register SMP Target Register Map Offset LSISASx12 Expander SAS Address High LSISASx12 Expander SAS Address Low Remote Routing Table Configuration Remote Routing Table Configuration Remote Routing Table Configuration Remote Routing Table Configuration Remote Routing Table Confi ...
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... This register provides the upper 32 bits of the 64-bit value that is used in the LoadID request from the SMP Target to the Expander Connection Manager LSISASx12 Expander SAS Address Low Expander SAS Address Low This register provides the lower 32 bits of the 64-bit value that is used in the LoadID request from the SMP Target to the Expander Connection Manager ...
Page 152
... The SMP Target uses these registers to convert a phy identifier and route index from the SMP REPORT ROUTE INFORMATION and CONFIGURE ROUTE INFORMATION commands into a local LSISASx12 address corresponding to a specific location within the remote route table. Each of these registers generates an output that informs each of the 12 Sphynx modules if the routing attribute of their associated phy is set to Table Route ...
Page 153
... SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Link Registers provides the register map for the SPhynx Link registers. Sphynx Link Register Map Identify Address Information Identify SAS Address High Identify SAS Address Low Discover Information 1 Discover Information 2 – ...
Page 154
... Register: 0x0004 Read/Write 4-76 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Sphynx Link Register Map (Cont.) Register Name SATA Dev2Host FIS3 Affiliated STP Initiator Address High Affiliated STP Initiator Address Low Phy Control Link Rates Phy Control PPTOV ...
Page 155
... For normal operation, leave this bit at its default setting. SMP Target Setting this bit configures the device as an SMP Target. For normal operation, leave this bit at its default setting. Reserved SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. [27:24] [23:12 ...
Page 156
... Identify SAS Address High SAS Address High This field provides bits [63:32] of the LSISASx12 64-bit SAS address Identify SAS Address Low SAS Address Low This field provides bits [31:0] of the LSISASx12 64-bit SAS address. Set the lower nibble of this register to 0xF Discover Information 1 Reserved ...
Page 157
... Attached SMP Initiator When set, this read-only bit indicates that the attached device is an SMP initiator. Reserved SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Definition No Device Attached End Device Only Edge Expander Device Fanout Expander Device Defi ...
Page 158
... When set, this read-only bit indicates that the attached device is a SATA target Discover Information 2 SAS Address High This read-only field provides bits [63:32] of the LSISASx12 SAS address Discover Information 3 SAS Address Low This read-only field provides bits [31:0] of the LSISASx12 SAS address ...
Page 159
... Register: 0x0058 Read/Write SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Discover Information 4 Attached SAS Address High This read-only field provides bits [63:32] of the attached SAS address Discover Information 5 Attached SAS Address Low This read-only field provides bits [31:0] of the attached SAS address ...
Page 160
... Register: 0x0060 Read/Write 4-82 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Reserved Reserved 16 15 Discover Information8 Programmed Minimum Physical Link Rate This field is read-only. Hardware Minimum Physical Link Rate This field is read-only. Programmed Maximum Physical Link Rate This fi ...
Page 161
... Register: 0x0068 Read/Write SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Reserved PPTOV This read-only field provides the partial pathway timeout value (PPTOV Discover Information 9 Reserved Routing Attribute This field provides the routing attributes, as defined in the SAS standard ...
Page 162
... Register: 0x0078 Read Only 4-84 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Report SATA Phy ID Reserved Phy Identifier This read-only field provides the Phy ID. Reserved Affiliations Supported This read-only bit indicates if affiliations are supported. ...
Page 163
... Register: 0x0080 Read Only SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved SATA Target Address Low SATA Target Address Low This read-only field provides bits [31:0] of the SATA target address SATA Dev2Host FIS0 FIS Type This field provides the FIS type. If the FIS type is 0x34, all Device-to-Host FISes are valid ...
Page 164
... Register: 0x0088 Read Only 4-86 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved SATA Dev2Host FIS1 Sector Number This read-only field provides the value of the sector number register in the shadow register block. Cyl Low This read-only field provides the value of the cylinder low register in the shadow register block ...
Page 165
... Register: 0x0098 Read/Write SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Cyl High (exp) This read-only field provides the value of the expanded cylinder high register in the shadow register block. Reserved 16 15 SATA Dev2Host FIS3 Sector Count This read-only field provides the value of the sector count register of the shadow register block ...
Page 166
... Register: 0x00A0 Read/Write 4-88 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Affiliated STP Initiator Address Low Affiliated STP Initiator Address Low This read-only field provides bits [31:0] of the affiliated STP initiator address Phy Control Link Rates Programmed Minimum Physical Link Rate This fi ...
Page 167
... Register: 0x00A4 Read/Write Register: 0x00AC Read/Write SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Phy Control PPTOV Reserved Partial Pathway Timeout Value This field programs the partial pathway timeout value (PPTOV). Reserved 16 15 Connection Information Reserved Align Count This read-only fi ...
Page 168
... To generate a broadcast primitive, write the attached address of the phy that originates a broadcast request to 4-90 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Reserved Connection Open This read-only bit indicates is set if a connection is open. ...
Page 169
... Broadcast SES registers, no broadcast primitive is transmitted on that link. SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Broadcast Change Low Address This field provides lower 32 bits of the 64-bit SAS address of the most recent Broadcast Change register written ...
Page 170
... Register: 0x0108 Read/Write 4-92 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Broadcast SES Low This field provides lower 32 bits of the 64-bit SAS address of the most recent Broadcast SES register written SATA Nexus Loss Timeout Reserved Nexus Loss Timeout Value (ms) This fi ...
Page 171
... SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. It also starts counting in the event of an OpenTimeout. Receipt of an OPEN_REJECT(RETRY/CONTINUE_/CONTINUE_1) frame resets and disables the nexus timer SATA Connection Mode Reserved ...
Page 172
... PhySMPOp Writing to this field initiates commands as outlined in Table 4.8. The LSISASx12 clears this bit field when the respective command completes. If the current command does not complete before writing a new command to this field, then the old command aborts and the new com- mand initiates ...
Page 173
... Register: 0x001C Read/Write SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Error Log Invalid Word Error Log Invalid Word This register indicates the number of invalid words received. This register increments when an invalid word is received while the PhyReady signal is asserted. ...
Page 174
... Read/Write 4-96 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Error Log Loss of Sync Error Log Loss of Synchronization This register indicates the number of loss-of-synchroniza- tion occurrences. This register increments when a loss of synchronization condition is reported outside of a reset sequence and following word synchronization ...
Page 175
... Select Pattern Description 0 SPhynx Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Test Register Reserved RX Jitter Enable Setting this bit enables receive jitter pattern checking. TX Jitter Enable Setting this bit enables transmit jitter pattern generation. JPAT Select This field specifies the jitter pattern for transmit genera- tion and receive checking. ing for this fi ...
Page 176
... Gbits/s All others encodings of this field are reserved. Force SATA Setting this bit causes the LSISASx12 to report as a SATA device. Use this bit in conjunction with the Bypass Reset Sequence bit. Select Starting Disparity This bit selects the starting disparity to be transmitted in the encoder when the LSISASx12 transitions from IDLE ...
Page 177
... STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. JitterReg When set to pattern 7, the jitter engine uses this value. Use this field to generate a “clock” pattern of various fre- quencies to assist in jitter measurements. The upper and lower halves of this register are fl ...
Page 178
... Base Address of 0x18000. However, only use this mechanism to write to the SATA Nexus Loss Timeout 4-100 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. STP Target Register Map (Cont.) Register Name SATA Dev2Host Reset FIS3 Affiliated STP Initiator Address High Affi ...
Page 179
... This field is written with the same value as Configuration Manager LSISASx12 Expander SAS Address High ter Expander SAS Address Low Expander SAS Address Low This field is written with the same value as Configuration Manager LSISASx12 Expander SAS Address High register Discover Information Reserved ...
Page 180
... Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Attached Device Type This read-only field provides the attached device type. The encoding of this field is Encoding 0b000 No Device Attached 0b001 0b010 Edge Expander Device 0b011 Fanout Expander Device All other encodings are reserved ...
Page 181
... Read/Write STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Attached SATA Port Selector When set, this read-only bit indicates that the attached device is a SATA port selector. Attached SSP Target When set, this read-only bit indicates that the attached device is an SSP target ...
Page 182
... Register: 0x0054 Read/Write 4-104 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Discover Information 3 SAS Address Low This read-only field provides bits [31:0] of the SAS address Discover Information 4 Attached SAS Address High This read-only field provides bits [63:32] of the attached SAS address ...
Page 183
... Register: 0x005C Read/Write Register: 0x0060 Read/Write STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Discover Information 6 Attached Phy Identifier This read-only field provides the attached phy identifier. Reserved 16 15 Reserved Reserved 16 15 Discover Information 8 Programmed Minimum Physical Link Rate This fi ...
Page 184
... Read/Write 4-106 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Hardware Maximum Physical Link Rate This field is read-only. Phy Change Count This read-only field indicates the number of times that the STP Target has requested a BROADCAST(CHANGE) to the broadcast processor. This counter wraps to 0x00 when it reaches the maximum value of 0xFF ...
Page 185
... Register: 0x0068 Read/Write Register: 0x0070 Read/Write STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Information 10 Reserved Vendor Specifi Phy SATA Phy ID Reserved Phy Identifier This read-only field provides the phy identifier. Reserved Affiliations Supported This bit is read-only. Affi ...
Page 186
... If the signature value in these registers is set to 0x010114EB, the host recognizes that the device supports the ATAPI PACKET Feature 4-108 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved STP Target SAS Address High STP Target SAS Address High This read-only fi ...
Page 187
... REPORT PHY SATA function. Register: 0x0084 Read/Write STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Error This field is set to 0x01 if the device passes boot diag- nostics. Status This field is set to 0x00 if there is not an error. Reserved Interrupt This bit refl ...
Page 188
... Register: 0x008C Read/Write 4-110 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Sector Number This read-only field provides signature byte 1. This field is set to 0x01, indicating that this is a PACKET device SATA Dev2Host Reset FIS2 Reserved Cyl High (exp) ...
Page 189
... Register: 0x00A0 Read/Write STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Affiliated STP Initiator Address High Affiliated STP Initiator Address High This read-only field provides bits [63:32] of the affiliated STP initiator address Affiliated STP Initiator Address Low Affi ...
Page 190
... Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Reserved Programmed Maximum Physical Link Rate This read-only field programs the maximum physical link rate. The default value for this field is 0b1001, which indi- cates a maximum physical link rate of 3.0 Gbits/s. ...
Page 191
... Register: 0x0108 Read/Write STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Function Result This read-only field indicates that the phy supports SATA. The encoding of this field is Encoding Definition 0x00 Phy supports SATA. All other encoding of this field are reserved. ...
Page 192
... Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Nexus Loss Timeout Value (ms) This field sets the nexus loss timeout value in millisec- onds. When the nexus loss timer reaches the value in this field and when the next reject or OpenTimeout occurs, the STP/SATA bridge requests a new reset sequence. The default value for this fi ...
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... This register contains the contents of the second dword of a non-Data FIS that was received from an STP Initiator. The fields displayed here are for FIS Type field 0x27. STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Last H2D Register FIS Received Dword 0 Features This read-only fi ...
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... This register contains the contents of the fourth dword of a non-Data FIS that was received from an STP Initiator. The fields displayed here are for FIS Type field 0x27. 4-116 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Dev/Head Cyl High Cyl Low Sector Number ...
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... Register: 0x0310 Read/Write STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Reserved Sector Count (exp) Sector Count 16 15 STP Connection Control Reserved Force Bad CRC This field is for verifying the reaction of the STP Target to receiving R_ERR. The encoding of this field is Encoding Defi ...
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... SmpPhyOp Commands Phy Op 0x00 No Operation. 0x01 This command clears the Disable STP bit and resets the LSISASx12 STP target. 0x02 This command clears the Affiliation Valid and Disable STP bits, and resets the LSISASx12 STP target. 0x03 This command causes any Inbound Open Address Frames targeting the STP Target to receive OPEN_REJECT (NO DESTINATION) ...
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... Read Only STP Target Registers Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. dword between a pair of SATA_SOF and SATA_EOF primitives. This count does not increment when an ERROR primitive is detected because a different phy in the expander chain increments its Invalid Dword count. This register does not increment after reaching the maximum value of 0xFFFFFFFF. Writing 0x05 to the SmpPhyOp fi ...
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... Read Only 4-120 Register Descriptions Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Error Log Unexpected SYNC Count Error Log Unexpected SATA Sync Count This read-only field indicates the number of disparity error occurrences. This field increments when a SATA_SYNC primitive is detected while the STP Target is expecting a different primitive ...
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... The SEP I C master may retry the transfer. Unrecovered Data FIS The LSISASx12 sets this read-only bit when the STP Target receives an R_ERR primitive in response to a Data FIS transmission attempt. If this occurs, the STP Target transmits a CLOSE sequence to close the connection if the command was not a PACKET command ...
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... PIO Setup FIS. If this occurs, the STP Tar- get transmits a CLOSE sequence to close the connec- tion. Unsupported FIS Received The LSISASx12 sets this read-only bit when the STP Tar- get receives one of the following FIS Types: D2H Register FIS DMA Activate FIS ...