LSISASX12 LSI, LSISASX12 Datasheet - Page 220

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x508
Read/Write
4-142
7
0
0
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
0
0
Actual CRC
Pointer Hi byte for the transfer that had the header CRC
error.
Reserved
Boot Error Doorbell Interrupt
This LSISASx12 sets this bit when the boot sequencer
indicates that a boot up did not occur properly. Setting
this bit generates an interrupt to the SEP. Write a 1 to this
bit to clear it.
Transfer Length Error Doorbell Interrupt
The LSISASx12 sets this bit when the SEP transfers an
incorrect number of bytes during an I
transaction. Setting this bit generates an interrupt to the
SEP. Write a 1 to this bit to clear it.
Actual CRC
When CRC checking is enabled and the LSISASx12
detects a CRC error, this register contains the value of
the header or payload CRC that contains the error. The
Expected CRC
value. This register value remains latched until the CRC
error is cleared in the
0
0
register contains the expected CRC
0
Error Detection Control
0
0
2
C write or read
register.
[5:2]
[7:0]
1
0