LSISASX12 LSI, LSISASX12 Datasheet - Page 49

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

2.6.3
SGPIO Pattern Generation
LSISASx12A expander in the enhanced SGPIO mode.
the encoding of the SIO Control Select bit.
Table 2.8
This section describes how to program the enhanced SGPIO interface
on the LSISASx12A expander.
There are four programmable pattern definition registers that define the
LED blink pattern (SIO Pattern Definition 3-0). Pages
define these registers. The pattern definition registers are rotating shift
registers that shift to the right once per time interval. Each pattern
generator uses a unique, programmable 20-bit pattern and a time base
interval of either 25 ms or 100 ms. The Timebase bit in the pattern
definition register determines the time base interval for the given pattern
definition register.
Table 2.9
The
provide control of the minimum assertion time, maximum assertion time,
minimum deassertion time, and off time following a maximum assertion.
Several examples of programming the enhanced SGPIO interface follow.
Example 1 – This example uses the
create a repeating pattern of 125 ms ON and 125 ms OFF.
GPIO/LED and SIO Configuration
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
SIO Control Select
0
1
Timebase Bit Setting
0
1
–
–
Activity Stretch Control
Set the SIO Control Select bit in the
to 0b1 to enable the enhanced SGPIO interface.
Set the Timebase bit to 0b0 to program a 25 ms time base.
SIO Control Select Bit Encoding
Timebase Bit Definition
Table 2.9
Enhanced SGPIO Mode
Standard SGPIO Mode
Shift frequency
provides the definition of the Timebase bit.
register and
100 ms
25 ms
SIO Mode
SIO Pattern Definition 0
SIO Adapter Control
SIO Adapter Control
4-67
Table 2.8
through
register to
registers
register
defines
4-69
2-27