LSISASX12 LSI, LSISASX12 Datasheet - Page 110

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4098
RC/SC
4-32
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register records the master interrupt status of the most recently
issued command. The master interrupt status bits are cleared either
when read or when a new command is issued.
Status bits [15:4] are interrupt sources for the master interrupt. If
interrupts are enabled, the API2C signals an interrupt when one or more
of these bits are set.
R
TT
TL
RFL
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
API2C Master Interrupt Status
Reserved
These bits are reserved.
API2C T
This bit sets to 1 if the T
master controller is in control of the API2C interface.
This bit clears to 0 when this register is read.
API2C T
This bit sets to 1 if T
master controller is in control of the API2C interface.
This bit clears to 0 when this register is read.
Receive FIFO High Threshold Reached
This bit sets to 1 during a Manual, Automatic, or
Sequence receive transfer when the Receive FIFO con-
tains four bytes or more and the number of data bytes
remaining in the transfer is greater than the number of
free locations in the FIFO.
This bit clears to 0 when the above condition is no longer
true or when the command completes abnormally
(Receive FIFO is flushed).
16 15
TIMEOUT
LOW
LOW:MEXT
TIMEOUT
8 7
timer expires when the
timer expires when the
0
0 0 0 0
[31:16]
0
15
14
13
0
0