LSISASX12 LSI, LSISASX12 Datasheet - Page 111

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

TFL
SNS
SS
SCC
IP
TSS
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Transmit FIFO Low Threshold Reached
During a Manual or Automatic transmit transfer, this bit
sets to 1 when the Transmit FIFO contains three bytes or
less, and when the number of bytes remaining in the
transfer is greater than the number of data bytes in the
FIFO.
This bit clears to 0 when the above condition is no longer
true or when the command completes abnormally (Trans-
mit FIFO is flushed).
Transfer Completed — Stop Not Sent
This bit sets to 1 after a manual transfer command com-
pletes successfully (all data bytes sent/received). This bit
clears to 0 when it is read or when a new command is
issued.
Transfer Completed — Stop Sent
This bit sets to 1 when an Automatic Transfer or
Sequence Transfer command completes successfully.
This bit clears to 0 when it is read or when a new com-
mand is issued.
Stop Command Completed
This bit sets to 1 after the master controller completes a
Stop command. A delay occurs between the assertion of
this interrupt and the completion of the STOP on the
API2C interface. This bit clears to 0 when it is read or
when a new command is issued.
Illegal Parameter
This bit sets to 1 if an Automatic Transfer or Sequence
Transfer command is issued when the Master Transfer
Length is set to 0. This bit clears to 0 when it is read or
when a new command is issued.
Time-Out Occurred — Stop Sent
This bit is set if a transfer command times out. A time-out
occurs when a wait timer expires while
awaiting the next command
the Transmit FIFO is empty and transmit transfer
length has not been met
the Receive FIFO is full and receive transfer length
has not been met
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