LSISASX12 LSI, LSISASX12 Datasheet - Page 103

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4050
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register issues commands to the master state machine.
R
SC
CT
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Reserved
These bits are reserved.
Send Command
When software sets this bit, the master state machine
issues the command that the command type field speci-
fies. After the bit is set, it remains set until the command
completes, and automatically clears when the command
completes.
After a command is in progress, the API2C core ignores
any write attempts to the command bit or to the com-
mand type field. If the software attempts to set this bit
when the command type field contains a reserved com-
mand type, this bit does not set.
Command Type
There are five commands the master state machine can
execute.
CT
000
001
010
011
100 – 110
111
API2C Master Command
Flushes (reset pointers) the Transmit and Receive
FIFOs
16 15
Function
Manual Mode Transfer
Automatic Mode Transfer
Sequence Mode Transfer
Issue Master Stop
Reserved
Flush Master Transmit FIFO
8 7
0
0 0 0 0
[31:4]
0
[2:0]
4-25
0
0
3