LSISASX12 LSI, LSISASX12 Datasheet - Page 114

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x40A8
Read Only
Register: 0x4100
Read/Write
4-36
31
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register keeps track of the number of successfully received
(acknowledged) data bytes.
R
NBR
This register sets up the clock based on the 75 MHz PCLK frequency. It
is configured automatically during system initialization. It is not necessary
to program this register.
This register determines the high period for the SCL clock generated by
API2C master state machine. The value specifies the number of PCLK
cycles that the SCL clock is HIGH.
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
24 23
API2C Receive Bytes Transferred
Reserved
These bits are reserved.
Number of Bytes Received
This field counts the number of acknowledged data bytes
that are transferred in the receive direction. The register
clears each time a start or repeated start occurs, and
counts the data bytes that are transferred after the
address phase of an API2C transaction. If a data transfer
stops due to an abnormal termination, the software can
use the value in this register to determine how to com-
plete the transfer.
API2C SCL High Period
16 15
16 15
8 7
8 7
0
0
0 0 0 0
0 0 0 0
[31:8]
0
0
[7:0]
0
0
0
0