LSISASX12 LSI, LSISASX12 Datasheet - Page 214

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

4-136
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Packet Command Received
This bit indicates that an ATA Packet command was
received. The Data FIS RAM contains the CDB for the
Packet command.
The STP-SEP Transfer Length register contains the Byte
Count Limit parameter of the Packet command. A
non-zero value indicates the number of dwords that can
be transferred in each Data FIS required to complete the
Packet command. A value of 0x00 indicates that up to
256 dwords (1 Kbyte) can be transferred at a time.
If the CDB indicates a data-out operation the SEP sets
the SEP-STP Transfer Length Register with the value of
the Byte Count Limit. The SEP-STP Transfer Attributes
register indicates the data direction and whether or not
the next data transfer is the last transfer for the Packet
command. The SEP sets the Packet Command Acknowl-
edge bit of the SEP-STP Doorbell register.
If the CDB indicates a data-in operation the SEP sets the
SEP-STP Transfer Attributes register to indicate the data
direction and whether or not the next data transfer is the
last transfer for the Packet command. After transferring
the appropriate data to the Data FIS RAM, the SEP sets
the Read Data Ready bit of the SEP-STP Doorbell Reg-
ister. The Packet Command Acknowledge bit is not set for
write operations.
If the CDB has an unsupported command or invalid
parameters, the SEP writes the Command Status register
with a Sense Key of “ILLEGAL REQUEST” (0x05) and
sets the Command Status Ready bit of the SEP-STP
Doorbell Register.
0