LSISASX12 LSI, LSISASX12 Datasheet - Page 136

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0xC008
Read/Write
Register: 0xC00C
Read/Write
4-58
31
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
24 23
SIO General Purpose Receive 0
Reserved
SIO Receive 1
When the SIO Device Count is set to 10 or 11, bit 0 of
this register contains bit 32 from the SioDin line and bits
[3:1] of this register are reserved. When SIO Device
Count is set to 11, bits [3:0] of this register contain bits
[35:32] from the SioDin line.
SIO General Purpose Receive 0
The SIO receive registers (SIO_RCV0 and SIO_RCV1)
receive data directly from the serial SIO at the end of
each normal serial input/output cycle. The number of bits
shifted in (and therefore the number of valid inputs bits)
is 3 times the SIO Device Count. The SIO Device Count
is located in the
Bits [(((SioDeviceCnt) * 3) – 1):0] of this register contain
the data shifted in during the most recent serial input/out-
put cycle. When the SIO Device Count is set to 10 or 11,
bits [31:0] of this register contain the data from bits [31:0]
of the input shift register, and the rest of the bits are avail-
able in the
SIO Receive 1
16 15
16 15
SIO General Purpose Receive 1
SIO Configuration
8 7
8 7
register.
0
0
0 0 0 0
0 0 0 0
register.
[31:4]
[31:0]
0
0
[3:0]
0
0
0
0