LSISASX12 LSI, LSISASX12 Datasheet - Page 134

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

4-56
Equation 4.1
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
The first input bit of the receive cycle must be ignored.
Do not set this field to a value less than 2 when SIO
Mode is set to a 1.
SIO Run Enable
This bit enables transmit and receive operations on the
SIO interface. Resets disable transmit and receive oper-
ations on the SIO interface until this bit is set. Once
enabled, transmit and receive operations continue until
this bit is cleared. Any transmit and receive operation in
progress when this bit is cleared continue to completion.
Clock Divide
This field sets the clock divide value for the SioClk clock
generation logic.
SioClk.
Frequency = 75 MHz 2((Clock Divide
The lowest frequency available is approximately 143 Hz.
The highest operational frequency is 200 KHz.
SIO Control ODEn
Setting this bit drives SioClk and SioEnd LOW, but per-
mits them to float HIGH. Clearing this bit drives SioClk
and SioEnd to both the HIGH and the LOW states.
SIO Clock Filter Enable
Setting this bit causes clock filtering of the selected Sio-
Clk.
Jog Activity
Setting this bit causes bits representing the Activity signal
in the serial bit stream to deassert for 256 ms after they
assert for 4 seconds. Clearing this bit allows these bits to
stay asserted for as long as the Active input remains in
the asserted state.
Clock Enable
Setting this bit configures the SioClk and BlinkClk internal
signals as inputs. Clearing this bit configures these sig-
nals as outputs.
Equation 4.1
provides the frequency of
8) + 1)
[21:7]
22
6
5
4
3