SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 214

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.6.1
Name:
Address:
Access:
Reset:
• MODE: SDRAMC Command Mode
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
214
0
0
0
0
1
1
1
MODE
31
23
15
–
–
–
7
–
0
0
1
1
0
0
1
SAM9G10
SDRAMC Mode Register
0
1
0
1
0
1
0
Description
Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be
followed by a write to the SDRAM.
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the
cycle. To activate this mode, command must be followed by a write to the SDRAM.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed
regardless of the cycle. Previously, an “All Banks Precharge” command must be issued. To activate this
mode, command must be followed by a write to the SDRAM.
The SDRAM Controller issues an “Extended Load Mode Register” command when the SDRAM device is
accessed regardless of the cycle. To activate this mode, the “Extended Load Mode Register” command
must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank;
most low-power SDRAM devices use the bank 1.
Deep power-down mode. Enters deep power-down mode.
30
22
14
SDRAMC_MR
0xFFFFEA00
Read-write
0x00000000
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
6462B–ATARM–6-Sep-11
24
16
–
–
8
–
0