SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 616

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
37.6
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write
operations to the UDP registers including the UDP_TXVC register.
Table 37-5.
Notes:
618
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030 + 0x4 * (ept_num - 1)
0x050 + 0x4 * (ept_num - 1)
0x070
0x074
0x078 - 0xFC
USB Device Port (UDP) User Interface
1. Reset values are not defined for UDP_ISR.
2. See Warning above the
SAM9G10
Register Mapping
Register
Frame Number Register
Global State Register
Function Address Register
Reserved
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Interrupt Clear Register
Reserved
Reset Endpoint Register
Reserved
Endpoint Control and Status Register
Endpoint FIFO Data Register
Reserved
Transceiver Control Register
Reserved
”Register Mapping”
on this page.
Name
UDP_FRM_NUM
UDP_GLB_STAT
UDP_FADDR
UDP_IER
UDP_IDR
UDP_IMR
UDP_ISR
UDP_ICR
UDP_RST_EP
UDP_CSR
UDP_FDR
UDP_TXVC
(2)
Access
Read-only
Read-write
Read-write
Write-only
Write-only
Read-only
Read-only
Write-only
Read-write
Read-write
Read-write
Read-write
6462B–ATARM–6-Sep-11
Reset
0x0000_0000
0x0000_0010
0x0000_0100
0x0000_1200
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
(1)

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