SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 730

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.2
42.2.1
42.2.1.1
42.2.2
42.2.2.1
42.2.3
42.2.3.1
732
AT91SAM9G10 Errata - Revision A Parts
SAM9G10
Battery Backup
Bus Matrix
System Controller
Backup Overconsumption During AHB Masters Activity
Bus Matrix: Problem with Locked Transfers
SYSC: Possible Event Loss when Reading RTT_SR
Refer to
Conditions:
During AHB Masters activity (LCD DMA, USB Host DMA, etc.) the backup current can rise up to
12 µA @ 25⋅ C.
Figure 42-1 on page 732
when the main power supply is off. In active mode, the clocks of unused peripherals should be
disabled through the Power Management Controller to save power.
Figure 42-1. Schematic
Locked transfers are not correctly handled by the Bus Matrix and can lead to a system freeze
up. This does not concern ARM locked transfers.
Avoid other Bus Matrix masters locked transfers.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is
read, the corresponding bit might be cleared. This can lead to the loss of this event.
The software must handle an RTT event as interrupt and as the only source of the interrupt
source level 1.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Section 42.1 “Marking” on page
J1
CR1225
Z1
+
3V
shows how to feed the backup part of the chip from the battery only
MMBD1704A
R1
CR1
1K
731.
3V3
3
C1
100NF
MN1
R1100D121C
C2
100NF
VDDBU
6462B–ATARM–6-Sep-11