S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 111

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
bits 5-0
bit 7
bit 6
bits 2-0
Hardware Functional Specification
Issue Date: 01/02/02
VRTC/FPFRAME Start Position Register
REG[0Bh]
n/a
VRTC/FPFRAME Pulse Width Register
REG[0Ch]
VRTC Polarity
Select
FPFRAME Polarity Select
n/a
FPFRAME
Polarity
Select
0
1
Note
Note
VRTC/FPFRAME Start Position Bits [5:0]
For CRT and TFT/D-TFD, these bits specify the delay in lines from the start of the vertical non-dis-
play period to the leading edge of the VRTC pulse and FPFRAME pulse respectively. For passive
LCD, FPFRAME is automatically created and these bits have no effect.
VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1
The maximum start delay is 64 lines.
VRTC Polarity Select
This bit selects the polarity of the VRTC pulse to the CRT.
When this bit = 1, the VRTC pulse is active high.
When this bit = 0, the VRTC pulse is active low.
FPFRAME Polarity Select
This bit selects the polarity of the FPFRAME pulse to the TFT/D-TFD or passive LCD.
When this bit = 1, the FPFRAME pulse is active high for TFT/D-TFD and active low for passive.
When this bit = 0, the FPFRAME pulse is active low for TFT/D-TFD and active high for passive.
VRTC/FPFRAME Pulse Width Bits [2:0]
For CRT and TFT/D-TFD, these bits specify the pulse width of VRTC and FPFRAME respectively.
For passive LCD, FPFRAME is automatically created and these bits have no effect.
VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1
This register must be programmed such that
(REG[0Ah] bits [5:0] + 1)
For exact timing please use the timing diagrams in section 7.5
This register must be programmed such that
(REG[0Ah] bits [5:0] + 1)
VRTC/
FPFRAME
Start Position
Bit 5
n/a
Table 8-5: FPFRAME Polarity Selection
Passive LCD FPFRAME Polarity
VRTC/
FPFRAME
Start Position
Bit 4
n/a
active high
active low
(REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
(REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
VRTC/
FPFRAME
Start Position
Bit 3
n/a
VRTC/
FPFRAME
Start Position
Bit 2
VRTC/
FPFRAME
Pulse Width
Bit 2
TFT/D-TFD FPFRAME Polarity
VRTC/
FPFRAME
Start Position
Bit 1
VRTC/
FPFRAME
Pulse Width
Bit 1
active high
active low
VRTC/
FPFRAME
Start Position
Bit 0
VRTC/
FPFRAME
Pulse Width
Bit 0
X23A-A-001-14
S1D13505
Page 105
RW
RW