S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 36

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

MA[8:0]
MA9
MA10
MA11
Page 30
S1D13505
X23A-A-001-14
Pin Name
O
IO
IO
IO
Type
58, 60, 62,
64, 66, 67,
65, 63, 61
56
59
57
Pin #
Table 5-2: Memory Interface Pin Descriptions (Continued)
CO1
C/TS
1
C/TS
1
C/TS
1
Cell
0utput
0utput
0utput
0utput
RESET#
State
Multiplexed memory address - see Memory Interface Timing for
functionality.
This is a multi-purpose pin:
• For 2M byte DRAM, this is memory address bit 9 (MA9).
• For asymmetrical 512K byte DRAM, this is memory address bit 9
• For symmetrical 512K byte DRAM, this pin can be used as general
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See “Memory Interface Pin Mapping” for summary. See Memory
Interface Timing for detailed functionality.
This is a multi-purpose pin:
• For asymmetrical 2M byte DRAM this is memory address bit 10
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See “Memory Interface Pin Mapping” for summary. See Memory
Interface Timing for detailed functionality.
This is a multi-purpose pin:
• For asymmetrical 2M byte DRAM this is memory address bit 11
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See “Memory Interface Pin Mapping” for summary. See Memory
Interface Timing for detailed functionality.
(MA9).
purpose IO pin 3 (GPIO3).
(MA10).
can be used as general purpose IO pin 1 (GPIO1).
(MA11).
can be used as general purpose IO pin 2 (GPIO2).
Description
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 01/02/02