S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 524

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 12
4.2 S1D13505 Configuration
S1D13505
X23A-G-010-04
MD0
MD[3:1]
MD4
MD5
MD11
MD12
S1D13505
Pin Name
111 = Toshiba TX3912 host bus interface if Alternate host bus interface is selected
Little Endian
WAIT# is active high (1 = insert wait state)
Alternate host bus interface selected
BUSCLK input divided by two: use with DCLKOUT
= configuration for Toshiba TX3912 host bus interface
The host interface control signals of the S1D13505 are asynchronous with respect to the
S1D13505 bus clock. This gives the system designer full flexibility to choose the
appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks
should be the same, whether to use DCLKOUT as clock source, and whether an external or
internal clock divider is needed, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13506 clock frequencies.
The S1D13505 also has internal CLKI dividers providing additional flexibility.
The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
The table below shows those configuration settings relevant to the Toshiba TX3912 host
bus interface.
Table 4-1: S1D13505 Configuration for Direct Connection
8-bit host bus interface
Value on this pin at rising edge of RESET# is used to configure:
1 (V
DD
)
16-bit host bus interface
Big Endian
WAIT# is active low (0 = insert wait state)
Primary host bus interface selected
BUSCLK input not divided: use with external oscillator
Interfacing to the Toshiba MIPS TX3912 Processor
Epson Research and Development
0 (V
SS
)
Vancouver Design Center
Issue Date: 01/02/05