S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 261

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Appendix A Supported Panel Values
A.1 Supported Panel Values
Programming Notes and Examples
Issue Date: 01/02/05
REG[0Ah]
REG[0Dh]
REG[1Bh]
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[08h]
REG[09h]
REG[19h]
REG[24h]
REG[26h]
Register
REG[0Ah]
REG[0Dh]
REG[1Bh]
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[08h]
REG[09h]
REG[19h]
REG[24h]
REG[26h]
Register
320X240@60Hz
Mono 4-Bit
0000 0000
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
load LUT
Table 12-1: Passive Single Panel @ 320x240 with 40MHz Pixel Clock
Table 12-2: Passive Single Panel @ 640x480 with 40MHz Pixel Clock
Note
The following tables show related register data for different panels. All the examples are
based on 8 bpp and 2M bytes of 50 ns EDO-DRAM.
640X480@60Hz
Mono 8-Bit
0001 0000
0000 0000
0100 1111
0000 0011
1101 1111
0000 0001
0000 0010
0000 1101
0000 0001
0000 0001
0000 0000
load LUT
The following settings may not reflect the ideal settings for your system configuration.
Power, speed, and cost requirements may dictate different starting parameters for your
system (e.g. 320x240@78Hz using 12MHz clock).
320X240@60Hz
Mono 4-Bit
1000 0000
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
load LUT
EL
640X480@60Hz
Color 8-Bit
0001 0100
0000 0000
0100 1111
0000 0011
1101 1111
0000 0001
0000 0010
0000 1101
0000 0001
0000 0001
0000 0000
load LUT
320X240@60Hz
Color 8-Bit
0001 0100
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
load LUT
640X480@60Hz
Color 16-Bit
0010 0100
0000 0000
0100 1111
0000 0011
1101 1111
0000 0001
0000 0010
0000 1101
0000 0001
0000 0001
0000 0000
load LUT
320X240@60Hz
Color 8-Bit
0001 1100
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
Format 2
load LUT
set vertical display height bits 7-0
set vertical display height bits 9-8
set horizontal non-display period
set Look-Up Table address to 0
set vertical non-display period
set MCLK and PCLK divide
set horizontal display width
set 8 bpp and LCD enable
disable half frame buffer
load Look-Up Table
set vertical display height bits 7-0
set vertical display height bits 9-8
set horizontal non-display period
set Look-Up Table address to 0
set vertical non-display period
set panel type
set MCLK and PCLK divide
set MOD rate
set horizontal display width
set 8 bpp and LCD enable
disable half frame buffer
Notes
load Look-Up Table
set panel type
set MOD rate
Notes
X23A-G-003-07
S1D13505
Page 107