S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 59

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/02/02
Symbol
t11
t10
t12
t13
t7
t1
t2
t3
t4
t5
t6
t8
t9
1
2
Clock period
Clock pulse width high
Clock pulse width low
A[20:0], M/R# setup to first CLK where CS# = 0 and either
RD0#,RD1#,WE0# or WE1# = 0
A[20:0], M/R# hold from rising edge of either RD0#,RD1#,WE0# or
WE1# = 0
CS# hold from rising edge of either RD0#,RD1#,WE0# or WE1# = 0
Falling edge of either RD0#,RD1#,WE0# or WE1# to WAIT# driven low
Rising edge of either RD0#,RD1#,WE0# or WE1# to WAIT# tri-state
D[15:0] setup to third CLK where CS# = 0 and WE0#,WE1# = 0 (write
cycle)
D[15:0] hold (write cycle)
Falling edge RD0#,RD1# to D[15:0] driven (read cycle)
D[15:0] setup to rising edge WAIT# (read cycle)
Rising edge of RD0#,RD1# to D[15:0] tri-state (read cycle)
1.
2.
If the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the
falling edge of RD0#, RD1#, WE0#, WE1# or the first positive edge of CLK after A[20:0],
M/R# becomes valid, whichever one is later.
If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD0#, RD1# or the first positive edge of CLK after A[20:0], M/R# becomes valid,
whichever one is later.
Parameter
Table 7-6: Generic Timing
Min
20
10
10
6
6
0
0
0
5
0
0
0
5
3.0V
Max
15
25
25
Min
2.5
20
10
10
6
6
0
0
0
0
0
0
5
5.0V
Max
X23A-A-001-14
10
10
10
S1D13505
Page 53
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