S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 115

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
REG[16h] bits 7-0
REG[17h] bits 2-0
bits 7-4
bits 3-0
Hardware Functional Specification
Issue Date: 01/02/02
Memory Address Offset Register 0
REG[16h]
Memory
Address
Offset Bit 7
Memory Address Offset Register 1
REG[17h]
n/a
Pixel Panning Register
REG[18h]
Screen 2
Pixel Panning
Bit 3
Memory
Address
Offset Bit 6
n/a
Screen 2
Pixel Panning
Bit 2
Display Mode
15/16 bpp
This register is used to control the horizontal pixel panning of Screen 1 and Screen 2. Each screen
can be independently panned to the left by programming its respective Pixel Panning Bits to a non-
zero value. The value represents the number of pixels panned. The maximum pan value is dependent
on the display mode.
Smooth horizontal panning can be achieved by a combination of this register and the Display Start
Address registers.
Memory Address Offset Bits [10:0]
These bits form the 11-bit address offset from the starting word of line n to the starting word of line
n+1. This value is applied to both Screen 1 and Screen 2.
Note that this value is in words.
A virtual image can be formed by setting this register to a value greater than the width of the dis-
play. The displayed image is a window into the larger virtual image.
See “Section 10 Display Configuration” for details.
See “Section 10 Display Configuration” for details.
Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
1 bpp
2 bpp
4 bpp
8 bpp
Memory
Address
Offset Bit 5
n/a
Screen 2
Pixel Panning
Bit 1
Table 8-8: Pixel Panning Selection
Memory
Address
Offset Bit 4
n/a
Screen 2
Pixel Panning
Bit 0
Maximum Pan Value
16
8
4
1
0
Memory
Address
Offset Bit 3
n/a
Screen 1
Pixel Panning
Bit 3
Memory
Address
Offset Bit 2
Memory
Address
Offset Bit 10
Screen 1
Pixel Panning
Bit 2
Pixel Panning Bits active
Bits [3:0]
Bits [2:0]
Bits [1:0]
none
Bit 0
Memory
Address
Offset Bit 1
Memory
Address
Offset Bit 9
Screen 1
Pixel Panning
Bit 1
Memory
Address
Offset Bit 0
Memory
Address
Offset Bit 8
Screen 1
Pixel Panning
Bit 0
X23A-A-001-14
S1D13505
Page 109
RW
RW
RW