S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 123

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
bit 6-5
bits 4-0
8.2.8 Look-Up Table Registers
bits 7-0
Hardware Functional Specification
Issue Date: 01/02/02
Look-Up Table Address Register
REG[24h]
LUT Address
Bit 7
LUT Address
Bit 6
Note
For example, writing a value 03h into the LUT Address Register sets the pointer to R[3]. A subse-
quent access to the LUT Data Register accesses R[3] and moves the pointer onto G[3]. Subsequent
accesses to the LUT Data Register move the pointer onto B[3], R[4], G[4], B[4], R[5], etc. Note that
the RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be
written before the LUT is updated.
CPU to Memory Wait State Bits [1:0]
These bits are used to optimize the handshaking between the host interface and the memory con-
troller. The bits should be set according to the relationship between BCLK and MCLK – see the
table below where T
Display FIFO Threshold Bits [4:0]
These bits specify the display FIFO depth required to sustain uninterrupted display fetches. When
these bits are all “0”, the display FIFO depth is calculated automatically.
These bits should always be set to 0, except in the following configurations:
When in the above configurations, a value of 1Bh should be used.
LUT Address Bits [7:0]
These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13505 has three 256-posi-
tion, 4-bit wide LUTs, one for each of red, green, and blue – refer to “Look-Up Table Architecture”
for details.
This register selects which LUT entry is read/write accessible through the LUT Data Register
(REG[26h]). Writing the LUT Address Register automatically sets the pointer to the Red LUT.
Accesses to the LUT Data Register automatically increment the pointer.
Wait State Bits [1:0]
The utility 13505CFG will, given the correct configuration values, automatically generate the
correct values for the Performance Enhancement Registers.
LUT Address
Bit 5
Landscape mode at 15/16 bpp (with MCLK=PCLK),
Portrait mode at 8/16 bpp (with MCLK=PCLK).
00
01
10
11
Table 8-16: Minimum Memory Timing Selection
B
LUT Address
Bit 4
and T
M
are the BCLK and MCLK periods respectively.
LUT Address
Bit 3
no restrictions (default)
LUT Address
Bit 2
2T
Condition
undefined
undefined
M
- 4ns > T
B
LUT Address
Bit 1
LUT Address
Bit 0
X23A-A-001-14
S1D13505
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