S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 118

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 112
REG[1Ch] bits 7-0
REG[1Dh] bits 7-0
bit 3
bit 2
bit 1
S1D13505
X23A-A-001-14
MD Configuration Readback Register 0
REG[1Ch]
MD[7] Status
MD Configuration Readback Register 1
REG[1Dh]
MD[15]
Status
General IO Pins Configuration Register 0
REG[1Eh]
n/a
MD[6] Status
MD[14]
Status
n/a
rising edge of
MD[7:6] at
RESET#
MD[15:0] Configuration Status
These are read-only status bits for the MD[15:0] pins configuration status at the rising edge of
RESET#. MD[15:0] are used to configure the chip at the rising edge of RESET# – see Pin Descrip-
tions and Summary of Configuration Options for details.
Pins MA9, MA10, MA11 are multi-functional – they can be DRAM address outputs or general
purpose IO dependent on the DRAM type. MD[7:6] are used to identify the DRAM type and
configure these pins as follows:
These bits are used to control the direction of these pins when they are used as general purpose IO.
These bits have no effect when the pins are used as DRAM address outputs.
GPIO3 Pin IO Configuration
When this bit = 1, the GPIO3 pin is configured as an output pin.
When this bit = 0 (default), the GPIO3 pin is configured as an input pin.
GPIO2 Pin IO Configuration
When this bit = 1, the GPIO2 pin is configured as an output pin.
When this bit = 0 (default), the GPIO2 pin is configured as an input pin.
GPIO1 Pin IO Configuration
When this bit = 1, the GPIO1 pin is configured as an output pin.
When this bit = 0 (default), the GPIO1 pin is configured as an input pin.
00
01
10
11
MD[5] Status
MD[13]
Status
n/a
Table 8-11: MA/GPIO Pin Functionality
GPIO3
MD[4] Status
MD[12]
Status
n/a
MA9
MA9
MA9
MA9
MD[3] Status
MD[11]
Status
GPIO3 Pin
IO Config.
Pin Function
GPIO1
GPIO1
GPIO1
MA10
MA10
MD[2] Status
MD[10]
Status
GPIO2 Pin
IO Config.
GPIO2
GPIO2
GPIO2
MA11
MA11
Epson Research and Development
MD[1] Status
MD[9]
Status
GPIO1 Pin
IO Config.
Hardware Functional Specification
Vancouver Design Center
Issue Date: 01/02/02
MD[0] Status
MD[8]
Status
n/a
RW
RO
RO