S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 280
S1D13505
Manufacturer Part Number
S1D13505
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13505.pdf
(566 pages)
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Page 16
S1D13505
X23A-B-001-04
Panel Data Width
Single / Dual
Disable Dual Panel Buffer
Mono / Color
Format 2
FPLINE Polarity
FPFRAME Polarity
Selects the panel data width. Panel data width is the
number of bits of data transferred to the LCD panel on
each clock cycle and shouldn’t be confused with color
depth which determines the number of displayed colors.
When the panel type is STN, the available options are 4
bit, 8 bit, and 16 bit. When the panel type is TFT the
available options are 9 bit, 12 bit, and 18 bit.
Selects between a single or dual panel.
When the panel type is TFT, “Single” is automatically
selected and the “Dual” option is grayed out.
The Dual Panel Buffer is used with dual STN panels to
improve image quality by buffering display data in a
format directly usable by the panel.
This option is primarily intended for testing purposes. It
is not recommended that the Dual Panel Buffer be
disabled as a reduction of display quality results.
Selects between a monochrome or color panel.
Selects color STN panel format 2. This option is specif-
ically for configuring 8-bit color STN panels.
See the S1D13505 Hardware Functional Specification,
document number X23A-A-001-xx, for description of
format 1 / format 2 data formats. Most new panels use
the format 2 data format.
Selects the polarity of the FPLINE pulse.
Refer to the panel specification for the correct polarity
of the FPLINE pulse.
Selects the polarity of the FPFRAME pulse.
Refer to the panel specification for the correct polarity
of the FPFRAME pulse.
Epson Research and Development
13505CFG Configuration Program
Vancouver Design Center
Issue Date: 01/03/29
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