r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1164

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Rev. 2.00 Dec. 09, 2005 Page 1140 of 1152
REJ09B0191-0200
Item
Table 15.8 Maximum Bit Rates
with External Clock Input
(Clocked Synchronous Mode, t
= 12t
Table 16.2 Register Configuration 788
16.3.5 I
(ICSR)
16.3.8 I
Register (ICDRR)
pcyc
)
2
2
C Bus Status Register
C Bus Receive Data
Scyc
Page Revision (See Manual for Details)
749
799
802
Amended.
Amended.
Amended and added.
Amended.
R/W → R
Pφ (MHz)
5
8
16
24
28.7
30
33
Register Name
I
Bit
3
2
C bus transmit data register
Bit Name Description
STOP
External Input
Clock (MHz)
0.4166
0.6666
1.3333
2.0000
2.3916
2.5000
2.7500
Stop Condition Detection Flag
[Clearing condition]
[Setting conditions]
When 0 is written in STOP after
reading STOP = 1
In master mode, when a stop
condition is detected after frame
transfer
In slave mode, when the slave
address in the first byte after the
general call and detecting start
condition matches the address set
in SAR, and then the stop
condition is detected
Maximum Bit
Rate (bits/s)
416666.6
666666.6
1333333.3
2000000.0
2391666.6
2500000.0
2750000.0
Initial Value
H'FF

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