r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 58

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
2.2
2.2.1
Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits)
or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a
register.
2.2.2
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in
8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored
in a register in sign-extended or zero-extended form.
A word operand should be accessed at a word boundary (an even address of multiple of two bytes:
address 2n), and a longword operand at a longword boundary (an even address of multiple of four
bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any
address.
Only big-endian byte order can be selected for the data format.
Data formats in memory are shown in figure 2.5.
Rev. 2.00 Dec. 09, 2005 Page 34 of 1152
REJ09B0191-0200
Data Formats
Data Format in Registers
Data Formats in Memory
Address 2n
Address 4n
31
Figure 2.5 Data Formats in Memory
Figure 2.4 Data Format in Registers
Address m
31
Byte
Word
Address m + 1
Longword
23
Byte
Longword
Address m + 2
15
Byte
Word
Address m + 3
7
Byte
0
0