r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 215

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

7.3.4
(1)
In a write access in write-back mode, the data is written to the cache and no external memory
write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit
way becomes the latest.
In write-through mode, the data is written to the cache and an external memory write cycle is
issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way
becomes the latest.
(2)
In write-back mode, an external bus cycle starts when a write miss occurs, and the entry is
updated. The way to be replaced follows table 7.4. When the U bit of the entry to be replaced is 1,
the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written
to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way
becomes the latest. After the cache completes its update cycle, the write-back buffer writes the
entry back to the memory. The write-back unit is 16 bytes.
In write-through mode, no write to cache occurs in a write miss; the write is only to the external
memory.
7.3.5
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the cache completes to fetch the new entry, the write-back buffer writes
the entry back to external memory. During the write-back cycles, the cache can be accessed. The
write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 7.3
shows the configuration of the write-back buffer.
Write Hit
Write Miss
Write Operation (Only for Operand Cache)
Write-Back Buffer (Only for Operand Cache)
A (31 to 4):
Longword 0 to 3:
A (31 to 4)
Figure 7.3 Write-Back Buffer Configuration
Longword 0
Physical address written to external memory (upper three bits are 0)
One line of cache data to be written to external memory
Longword 1
Longword 2
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Longword 3
REJ09B0191-0200
Section 7 Cache