r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 64

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
2.3.2
Addressing modes and effective address calculation are as follows:
Table 2.8
Rev. 2.00 Dec. 09, 2005 Page 40 of 1152
REJ09B0191-0200
Addressing
Mode
Register direct
Register indirect @Rn
Register indirect
with post-
increment
Register indirect
with pre-
decrement
Addressing Modes
Addressing Modes and Effective Addresses
Instruction
Format
Rn
@Rn+
@-Rn
Effective Address Calculation
The effective address is register Rn. (The operand
is the contents of register Rn.)
The effective address is the contents of register Rn.
The effective address is the contents of register Rn.
A constant is added to the contents of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rn
Rn
Equation
—
Rn
Rn
(After
instruction
execution)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)