r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 777

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

15.3.10 FIFO Data Count Set Register (SCFDR)
SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR).
It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of
receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is
initialized to H'0000 by a power on reset.
Initial value:
Bit
15 to 13
12 to 8
7 to 5
4 to 0
R/W:
Bit:
Bit Name
—
T[4:0]
—
R[4:0]
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
00000
All 0
00000
12
R
0
11
R
0
R/W
R
R
R
R
T[4:0]
10
R
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
T4 to T0 bits indicate the quantity of non-transmitted
data stored in SCFTDR. H'00 means no transmit data,
and H'10 means that SCFTDR is full of transmit data.
Reserved
These bits are always read as 0. The write value should
always be 0.
R4 to R0 bits indicate the quantity of receive data
stored in SCFRDR. H'00 means no receive data, and
H'10 means that SCFRDR full of receive data.
Section 15 Serial Communication Interface with FIFO (SCIF)
R
9
0
R
8
0
R
7
0
-
Rev. 2.00 Dec. 09, 2005 Page 753 of 1152
R
6
0
-
R
5
0
-
R
4
0
R
3
0
REJ09B0191-0200
R[4:0]
R
2
0
R
1
0
R
0
0