r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 857

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
15
14
13
12
Bit Name
ADF
ADIE
ADST

Initial
Value
0
0
0
0
R/W
R/(W)* A/D End Flag
R/W
R/W
R
Description
Status flag indicating the end of A/D conversion.
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at the
end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
A/D Start
Starts or stops A/D conversion. This bit remains set to 1
during A/D conversion.
0: A/D conversion is stopped
1: Single mode: A/D conversion starts. This bit is
Reserved
This bit is always read as 0. The write value should
always be 0.
automatically cleared to 0 when A/D conversion ends
on the selected channel.
Multi mode: A/D conversion starts. This bit is
automatically cleared to 0 when A/D conversion is
completed cycling through the selected channels.
Scan mode: A/D conversion starts. A/D conversion is
continuously performed until this bit is cleared to 0 by
software, by a power-on reset, or by a transition to
software standby mode or module standby mode.
Cleared by reading ADF while ADF = 1, then writing
0 to ADF
Cleared when DMAC is activated by ADI interrupt
and ADDR is read
A/D conversion ends in single mode
A/D conversion ends for the selected channels in
multi mode
A/D conversion ends for the selected channels in
scan mode
Rev. 2.00 Dec. 09, 2005 Page 833 of 1152
Section 17 A/D Converter (ADC)
REJ09B0191-0200