r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 14

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Direct Memory Access Controller (DMAC)..................................... 357
9.1
9.2
9.3
9.4
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 407
10.1 Features.............................................................................................................................. 407
10.2 Input/Output Pins............................................................................................................... 413
10.3 Register Descriptions......................................................................................................... 414
Rev. 2.00 Dec. 09, 2005 Page xiv of xxiv
Features.............................................................................................................................. 357
Input/Output Pins............................................................................................................... 360
Register Descriptions......................................................................................................... 361
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
Operation ........................................................................................................................... 385
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
10.3.1 Timer Control Register (TCR).............................................................................. 418
10.3.2 Timer Mode Register (TMDR)............................................................................. 422
10.3.3 Timer I/O Control Register (TIOR)...................................................................... 425
10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 444
10.3.5 Timer Interrupt Enable Register (TIER)............................................................... 445
10.3.6 Timer Status Register (TSR)................................................................................. 450
10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 458
10.3.8 Timer Input Capture Control Register (TICCR)................................................... 459
10.3.9 Timer Synchronous Clear Register (TSYCR) ...................................................... 460
10.3.10 Timer A/D Converter Start Request Control Register (TADCR) ......................... 462
10.3.11 Timer A/D Converter Start Request Cycle Set Registers
10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
10.3.13 Timer Counter (TCNT)......................................................................................... 466
10.3.14 Timer General Register (TGR) ............................................................................. 466
DMA Source Address Registers (SAR)................................................................ 365
DMA Destination Address Registers (DAR)........................................................ 366
DMA Transfer Count Registers (DMATCR) ....................................................... 367
DMA Channel Control Registers (CHCR) ........................................................... 368
DMA Reload Source Address Registers (RSAR)................................................. 376
DMA Reload Destination Address Registers (RDAR)......................................... 377
DMA Reload Transfer Count Registers (RDMATCR) ........................................ 378
DMA Operation Register (DMAOR) ................................................................... 379
DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).................. 383
Transfer Flow........................................................................................................ 385
DMA Transfer Requests ....................................................................................... 387
Channel Priority.................................................................................................... 391
DMA Transfer Types............................................................................................ 394
Number of Bus Cycles and DREQ Pin Sampling Timing .................................... 403
(TADCORA_4 and TADCORB_4)...................................................................... 465
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 465