r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 398

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Direct Memory Access Controller (DMAC)
Rev. 2.00 Dec. 09, 2005 Page 374 of 1152
REJ09B0191-0200
Bit
7
6
5
4, 3
2
Bit Name
DL
DS
TB
TS[1:0]
IE
Initial
Value
0
0
0
00
0
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
DREQ Level
DREQ Edge Select
These bits specify the sampling method of the DREQ
pin input and the sampling level.
These bits are valid only in CHCR_0 to CHCR_3.
These bits are reserved in CHCR_4 to CHCR_7; they
are always read as 0 and the write value should
always be 0.
If the transfer request source is specified as an on-chip
peripheral module or if an auto-request is specified, the
specification by these bits is ignored.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
Note that the burst mode must not be selected when
TC = 0.
0: Cycle steal mode
1: Burst mode
Transfer Size
These bits specify the size of data to be transferred.
Select the size of data to be transferred when the
source or destination is an on-chip peripheral module
register of which transfer size is specified.
00: Byte unit
01: Word unit (two bytes)
10: Longword unit (four bytes)
11: 16-byte (four longword) unit
Interrupt Enable
Specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request
(DEI) to the CPU when TE bit is set to 1.
0: Disables an interrupt request
1: Enables an interrupt request